Conductive TSV SOI Structure Without Costly Wafer Bonding

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Solution Overview

Problem

The high cost of semiconductor-on-insulator (SOI) substrates due to the expensive bonding process hinders the widespread adoption of their performance benefits in integrated circuits (ICs).

Innovation Solution

A low-cost SOI structure is formed by depositing a metal layer over an insulating layer, eliminating the need for the expensive bonding process, and incorporating through-substrate vias (TSVs) for improved electrical connectivity and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional SOI bonding process is used, then semiconductor device performance is improved, but fabrication cost increases significantly

Engineering Contradiction:

Improvesemiconductor device performanceVSAvoidfabrication cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces the expensive traditional SOI bonding process with a cost-effective metal layer deposition approach. Instead of using costly bonding procedures, the invention employs standard semiconductor fabrication techniques (physical vapor deposition, chemical vapor deposition, or atomic layer deposition) to form metal layers that provide similar electrical isolation and device performance benefits at significantly lower fabrication costs

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The invention changes the fundamental approach from mechanical/thermal bonding to thin-film deposition by controlling deposition parameters such as layer thickness (50-500 nm), deposition temperature, and material composition. This parameter change enables achieving SOI substrate performance benefits through a different physical process that is more cost-effective and better integrated with standard CMOS fabrication

Inventive Principle:

Principle #35Parameter changes

2Ease of manufacture

If metal layer is deposited over insulating layer, then fabrication cost is reduced, but electrical connectivity may be affected

Engineering Contradiction:

Improvefabrication costVSAvoidelectrical connectivity

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the electrical connectivity path by creating separate dedicated pathways: through-substrate vias (TSVs) for vertical connections and metal interconnect layers for horizontal connections. This segmentation ensures that the metal layer deposited over the insulating layer does not interfere with electrical connectivity, as TSVs penetrate through the insulating layer to establish direct electrical pathways independent of the overlying metal deposition

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent uses TSVs as intermediary structures that mediate between the insulating layer and external electrical contacts. These TSVs act as conductive bridges that maintain electrical connectivity despite the presence of the metal layer deposited over the insulating layer, effectively decoupling the electrical connection function from the insulating function

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If through-substrate vias are incorporated, then electrical connectivity is improved, but device complexity increases

Engineering Contradiction:

Improveelectrical connectivityVSAvoidstructure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements multi-functional TSV structures that simultaneously serve multiple purposes: providing electrical connectivity, enabling back-side access for testing and packaging, facilitating 3D integration, and serving as alignment references for subsequent processing steps. This universality justifies the added structural complexity by delivering multiple performance benefits from a single feature

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The low-cost SOI structure achieves similar performance improvements to traditional SOI substrates, including reduced leakage current and increased switching speed, while significantly lowering fabrication costs.

Implementation Method 1

A low-cost SOI structure is formed by depositing a metal layer over an insulating layer

Methodology Applied

Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

A low-cost SOI structure is formed by depositing a metal layer over an insulating layer

Methodology Applied

Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS12408439B2Integrated chip (IC) having conductive TSV extended through SOI substrate comprising a semiconductor device layer, an insulating layer and a metal layer

Publication Date: 2025.09.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a substrate. The substrate includes a metal layer, a device layer disposed over the metal layer, and an insulating layer disposed vertically between the metal layer and the device layer. A semiconductor device is disposed on the device layer. An interlayer dielectric (ILD) layer is disposed over the semiconductor device and the substrate.