Conductive Via Formation for Void-Free 3D Memory Arrays
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Solution Overview
Problem
The challenge lies in forming tall conductive vias in integrated circuitry, particularly in vertically grown memory circuitry, where it is difficult to fill high-aspect-ratio contact openings without voids, which can reduce conductivity and lead to inoperable circuitry.
Innovation Solution
The method involves forming a conductive via through a stack of alternating insulative and conductive tiers, using a lining of elemental-form silicon over the opening, ion implanting the upper portion, reacting the lower portion with a metal halide to form elemental metal, and depositing conductive material directly against this metal, resulting in a crystalline metal via with different upper and lower phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional filling methods are used for high-aspect-ratio contact openings, then the opening can be filled, but voids form that reduce conductivity and may lead to inoperable circuitry
Solution Approach 1:
The patent changes the physical and chemical parameters of the filling process by using sequential deposition methods with controlled layer thicknesses and compositions. The conductive filling material is deposited in multiple layers with varying properties (e.g., different metal compositions, grain structures) to optimize flow and packing during filling, enabling complete void-free filling of high-aspect-ratio openings while maintaining circuit reliability
Solution Approach 2:
The patent employs composite conductive filling structures consisting of multiple material layers with different properties. These composite structures combine materials with complementary characteristics (e.g., different conductivities, melting points, flow properties) to achieve both complete filling of high-aspect-ratio openings and optimal electrical conductivity, resolving the contradiction between manufacturing precision and circuit reliability
2Length of moving object
If tall conductive vias are formed in vertically grown memory circuitry, then three-dimensional integration is achieved, but the high-aspect-ratio openings become difficult to fill without voids
Solution Approach 1:
The patent segments the filling process into multiple sequential deposition steps rather than attempting to fill the entire high-aspect-ratio opening in one operation. Each deposition step creates a manageable layer that can be properly formed without voids, and the cumulative effect of multiple layers achieves complete filling of the tall via while maintaining manufacturing feasibility
Solution Approach 2:
The patent performs preliminary actions by depositing preparatory layers with specific properties before the main conductive material. These preliminary layers modify the surface characteristics, promote better material flow, and prepare the opening geometry to facilitate subsequent filling steps, making the overall process of filling tall vias more manageable and less prone to void formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the formation of conductive vias with large grain size and minimal voids, enhancing conductivity and preventing inoperable circuitry, while allowing for direct electrical coupling without alternative processing.
Implementation Method 1
The elemental-form silicon of an uppermost portion of the lining is ion implanted in the elevationally-elongated opening
Implementation Method 2
The elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting is reacted with a metal halide to form elemental-form metal
Data Source
AI summary
A method used in forming a conductive via of integrated circuitry comprises forming a lining laterally over sidewalls of an elevationally-elongated opening. The lining comprises elemental-form silicon. The elemental-form silicon of an uppermost portion of the lining is ion implanted in the elevationally-elongated opening. The ion-implanted elemental-form silicon of the uppermost portion of the lining is etched selectively relative to the elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting. The elemental-form silicon of the lower portion of the lining is reacted with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide. Conductive material in the elevationally-elongated opening is formed atop and directly against the elemental-form metal. Other embodiments, including structure independent of method, are disclosed.