Conductive Via Backside Alignment for Smaller Semiconductor Components
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Solution Overview
Problem
The alignment of conductive vias in semiconductor components is becoming increasingly difficult due to their shrinking size, leading to issues with misalignment during fabrication, which can result in short circuits or open circuits.
Innovation Solution
A maskless back side alignment method is employed, where conductive vias are self-aligned by forming terminal portions that are encapsulated in a polymer layer and planarized, eliminating the need for a photo mask and reducing the risk of misalignment, allowing for smaller via diameters and preventing short or open circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional photo patterning processes are used to align conductive vias to back side elements, then the fabrication process is straightforward, but alignment precision deteriorates as via size shrinks
Solution Approach 1:
The conductive via itself serves as the alignment reference by protruding through the planarized substrate surface. The via structure automatically defines the alignment position for back side elements, eliminating the need for separate alignment marks or complex photo patterning alignment processes
Solution Approach 2:
The alignment problem is solved by transitioning from a 2D planar alignment approach to a 3D approach where the via protrudes above the substrate surface, creating a vertical dimension that provides inherent alignment reference for back side element formation
2Volume of moving object
If conductive vias are made smaller to enable further miniaturization, then component size is reduced, but alignment difficulty increases
Solution Approach 1:
The small conductive via automatically provides its own alignment reference by protruding through the planarized surface, eliminating the need for external alignment marks that would be even harder to align with smaller features
Solution Approach 2:
The via is formed and planarized beforehand to create a protruding structure that serves as a pre-established alignment reference, allowing subsequent back side elements to be formed with accurate alignment to the via position
3Ease of manufacture
If misalignment occurs during fabrication, then manufacturing is simpler, but electrical reliability deteriorates due to short or open circuits
Solution Approach 1:
The via structure itself provides the alignment reference, ensuring that back side elements are automatically aligned to the correct position, thereby preventing misalignment-induced short or open circuits
Solution Approach 2:
The protruding via structure provides a built-in alignment buffer that compensates for potential misalignment during back side element formation, preventing electrical connection failures before they occur
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures precise alignment of conductive vias, preventing short circuits and open circuits, while enabling the fabrication of smaller semiconductor components with improved electrical insulation and reduced fabrication complexity.
Implementation Method 1
The conductive vias are self-aligned by forming terminal portions that are encapsulated in a polymer layer and planarized
Data Source
AI summary
A semiconductor component includes a semiconductor substrate, conductive vias in the substrate having terminal portions, a polymer layer on the substrate and back side conductors formed by the terminal portions of the conductive vias embedded in the polymer layer. A stacked semiconductor component includes a plurality of components having aligned conductive vias in electrical communication with one another.