Conductive Via Bar Self-Aligned to Gate Ends
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, limiting further miniaturization beyond the 10 nanometer node, particularly in aligning conductive via bars with gate ends without compromising performance or increasing manufacturing complexity.
Innovation Solution
The implementation of a method to fabricate conductive via bars self-aligned to gate ends, utilizing a combination of non-selective metal gate and pre-spacer cut processes, which simplifies the fabrication of deep via bars and eliminates the need for critical lithography operations, enabling perfect or near-perfect self-alignment and reducing edge placement errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for multi-gate transistor scaling, then existing manufacturing infrastructure can be maintained, but manufacturing precision deteriorates at 10 nanometer node and below due to variability in aligning conductive via bars with gate ends
Solution Approach 1:
Dielectric spacers are formed around the gate structure before the conductive via bar formation process. These pre-formed spacers serve as alignment references that automatically define the precise location where conductive via bars will be deposited, eliminating the need for complex lithography alignment at the 10nm node and below.
Solution Approach 2:
The dielectric spacers self-align to the gate structure through conformal deposition processes, and subsequently serve as self-aligned masks or references for conductive via bar formation. This self-service mechanism ensures perfect alignment between via bars and gate ends without requiring additional alignment steps or complex lithography processes.
2Manufacturing precision
If critical lithography operations are used to align conductive via bars with gate ends, then alignment precision can be maintained, but manufacturing complexity and edge placement errors increase
Solution Approach 1:
Dielectric spacers act as intermediary structures that mediate between the gate structure and the conductive via bars. These spacers are formed through simple conformal deposition and serve as physical references that automatically define the precise location for via bar formation, replacing complex lithography alignment operations.
Solution Approach 2:
The patent replaces complex lithography-based mechanical alignment systems with a deposition-based self-aligned system. Instead of using lithography to precisely position via bars relative to gates, the method uses conformal dielectric spacer deposition followed by atomic layer deposition (ALD) to automatically achieve perfect alignment through physical self-reference.
3Area of moving object
If feature sizes are scaled down to increase device density, then capacity increases, but manufacturing precision deteriorates due to process variability at sub-10 nanometer nodes
Solution Approach 1:
The patent moves the alignment problem from the lateral (2D) dimension to the vertical (3D) dimension. Instead of aligning via bars to gates in the lateral plane using lithography, the method uses vertical conformal spacer deposition around the gate structure, where the spacer thickness and conformal nature automatically define the via bar position in three-dimensional space, achieving perfect alignment regardless of lateral feature size scaling.
Data Source
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AI summary
Conductive via bars self-aligned to gate ends are described. In an example, an integrated circuit structure includes a plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A conductive via bar is along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar.