Conductive Via Caps with Flanges for Microelectronic Insulation
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Solution Overview
Problem
The challenge in microelectronic device manufacturing lies in creating efficient through vias that allow for compact, high-performance, and cost-effective multi-chip stacked packages, where existing methods struggle with precise exposure and insulation of conductive vias, leading to issues with contamination and limited resolution in photolithography processes.
Innovation Solution
The implementation of a conductive via structure with a conductive cap and insulating layers, where the insulating layer body is thicker away from the via, and the cap extends across the via end surface with a flange along the sidewall, along with a dished substrate face and trenches, to enhance exposure and reduce contamination, allowing for improved planarization and connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional photolithography methods are used for via exposure, then manufacturing process is simple, but resolution and precision are limited leading to contamination issues
Solution Approach 1:
The patent applies preliminary action by forming the insulating layer with variable thickness and the conductive cap with flange structure before the final via exposure step. The insulating layer extension protruding onto the via sidewall and the cap flange extending along the sidewall create pre-defined exposure boundaries that guide the exposure process, enabling precise via formation without relying solely on conventional photolithography resolution
Solution Approach 2:
The patent implements local quality by creating non-uniform insulating layer thickness where the layer extension is thicker remote from the via compared to adjacent the via. This variable thickness profile provides different functions in different locations: the thinner region adjacent to the via allows precise exposure and connection, while the thicker region remote from the via provides enhanced insulation and structural support
2Reliability
If through vias are made deeper for better connection, then connection reliability improves, but exposure difficulty and contamination risk increase
Solution Approach 1:
The patent uses the insulating layer extension and conductive cap flange as intermediary structures that extend onto and along the via sidewall. These intermediaries create a protective barrier and defined boundary during the exposure process, preventing contamination from entering the deep via while still allowing the via to achieve sufficient depth for reliable connection
Solution Approach 2:
The patent transitions from a two-dimensional planar exposure approach to a three-dimensional structured exposure by forming the insulating layer extension and cap flange that wrap around the via sidewall. This dimensional change creates vertical boundaries and protected zones that enable precise exposure of deep vias while preventing contamination from lateral directions
3Reliability
If insulating layer thickness is uniform, then manufacturing is easier, but insulation performance and structural support are insufficient
Solution Approach 1:
The patent applies local quality by creating a variable thickness insulating layer where the thickness varies with distance from the via. The layer extension is configured to be thicker remote from the via compared to adjacent the via, providing enhanced insulation and structural support in regions where these functions are most needed, while maintaining manufacturability through a systematic thickness gradient
Data Source
AI summary
Microelectronic devices include a conductive via that extends into a substrate face and that also protrudes beyond the substrate face to define a conductive via end surface and a conductive via sidewall that extends from the end surface towards the substrate face. A conductive cap is provided on the end surface, the conductive cap including a conductive cap body that extends across the end surface and a flange that extends from the conductive cap body along the conductive via sidewall towards the substrate face. Related fabrication methods are also described.