Conductive Via in Encapsulation for Semiconductor Package
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Solution Overview
Problem
The challenge in semiconductor packaging is to miniaturize packages while maintaining reliability and process simplicity, as the size of electronics demands smaller, lighter, and more integrated components, with existing technologies struggling to achieve high-density connections and efficient manufacturing processes.
Innovation Solution
A semiconductor package design that includes a semiconductor chip, a conductive element, a conductive via, and an insulating encapsulation, where the conductive via is embedded within the encapsulation, allowing for efficient thinning of the insulating material and adjustable pitch between vias for high-density connections, and eliminating the need for a photo-lithography process for redistribution layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the conductive element height is reduced to be less than the semiconductor chip height, then the insulating material thinning process becomes more efficient, but the connection density and electrical performance may be compromised
Solution Approach 1:
The patent introduces a vertical dimension solution by forming conductive vias that extend downward from the insulating encapsulation surface to contact the conductive element. This via structure allows the conductive element to be positioned at a lower height while maintaining electrical connection through the vertical via path, thus resolving the contradiction between reduced height and connection reliability.
Solution Approach 2:
The conductive via acts as an intermediary element between the conductive element and the circuit structure. It bridges the height difference and enables electrical connection without requiring the conductive element surface to be at the same level as the chip active surface, thereby facilitating efficient thinning while maintaining connection integrity.
2Quantity of substance
If the pitch between conductive vias is reduced to achieve high-density connections, then the integration density increases, but the manufacturing precision and alignment difficulty increase
Solution Approach 1:
The conductive element is pre-formed with a specific pitch configuration before the insulating encapsulation is applied. This preliminary positioning establishes a template that guides the subsequent via formation process, enabling precise via placement at reduced pitch without requiring high-precision alignment during the via formation step itself.
Solution Approach 2:
The via pattern copies the underlying conductive element arrangement. By forming vias that align with the pre-established conductive element pitch, the design transfers the precise spacing relationship to the via layer, achieving high-density connections with controlled pitch through the copying of the lower-layer geometry.
3Ease of manufacture
If the photo-lithography process for redistribution layer is omitted, then the manufacturing cost and process complexity are reduced, but the routing flexibility and circuit design freedom are limited
Solution Approach 1:
The conductive via serves multiple functions: it provides electrical connection, enables pitch adjustment, and acts as a routing element without requiring separate photo-lithography processing. This multi-functionality allows the via structure to replace the traditional redistribution layer while maintaining routing capabilities through direct via-to-via or via-to-pad connections.
Solution Approach 2:
The patent extracts the photo-lithography step from the manufacturing process by using directly formed conductive vias instead of photolithographically patterned redistribution layers. This removal of the photo-lithography step simplifies the process and reduces cost while the via structure itself provides the necessary routing function through alternative means.
Data Source
AI summary
A semiconductor package including a semiconductor chip, a conductive element disposed aside the semiconductor chip, a conductive via disposed on and electrically connected to the conductive element, an insulating encapsulation, and a first circuit structure disposed on the semiconductor chip and the conductive via is provided. A height of the conductive element is less than a height of the semiconductor chip. The insulating encapsulation encapsulates the semiconductor chip, the conductive element, and the conductive via. The conductive via is located between the first circuit structure and the conductive element, and the semiconductor chip is electrically coupled to the conductive via through the first circuit structure.