Conductive Via Formation Without CVD Etching CMP
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Solution Overview
Problem
Existing semiconductor device manufacturing processes, particularly those involving through-silicon vias (TSVs), are time-consuming and costly due to the necessity of chemical vapor deposition (CVD), etching of silicon nitride layers, and chemical-mechanical planarization (CMP) stages after the reveal process.
Innovation Solution
The method involves forming conductive vias in semiconductor devices without the need for CVD, etching of silicon nitride layers, or CMP stages by using a specific sequence of materials and processes, including a conductive core, barrier material, dielectric materials, and interconnect formation, which omits these costly steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TSV manufacturing processes are used including CVD, etching of silicon nitride layers, and CMP stages, then reliable conductive via formation is achieved, but manufacturing time and production costs increase significantly
Solution Approach 1:
The patent extracts and eliminates unnecessary processing stages (CVD, silicon nitride etching, CMP) from the conventional TSV manufacturing process. By removing these extraneous steps while retaining the essential functions through alternative methods, the process achieves the same reliable conductive via formation with reduced cycle time and lower costs.
Solution Approach 2:
The patent performs preliminary actions by pre-forming the conductive core and barrier material structure before final via completion. This preliminary structuring allows subsequent steps to be simplified and eliminates the need for later CVD and CMP operations, thereby reducing overall manufacturing time while maintaining reliability.
2Manufacturing precision
If conventional TSV manufacturing processes including CVD, etching, and CMP stages are used, then proper material deposition and planarization are achieved, but production costs increase
Solution Approach 1:
The patent employs cheaper, simpler materials and processes that can be easily deposited and removed without requiring expensive CVD equipment or CMP operations. The use of alternative dielectric materials and barrier structures achieves the necessary precision at lower production costs.
Solution Approach 2:
The patent changes the parameters of the manufacturing process by using different deposition methods and material combinations that achieve the same functional results with lower cost. By modifying material selection and process parameters, precision is maintained while eliminating costly steps.
3Productivity
If simplified processes without CVD, etching, and CMP stages are used, then manufacturing cycle time and costs are reduced, but the complexity of achieving proper via structure increases
Solution Approach 1:
The patent merges multiple functions into fewer process steps. By combining the formation of conductive core, barrier material, and dielectric structures into an integrated process flow that eliminates separate CVD, etching, and CMP stages, the overall process complexity is managed while maintaining high productivity.
Solution Approach 2:
The patent performs preliminary structuring of the via components in advance, creating a pre-assembled structure that simplifies subsequent processing. This preliminary action reduces the complexity of later steps while enabling faster production.
Data Source
AI summary
Semiconductor devices having a conductive via and methods of forming the same are described herein. As an example, a semiconductor devices may include a conductive via formed in a substrate material, a barrier material, a first dielectric material on the barrier material, a coupling material formed on the substrate material and on at least a portion of the dielectric material, a second dielectric material formed on the coupling material, and an interconnect formed on the conductive via.