Conductive Via Layout Between Metal Gates to Cut Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The shrinking size of semiconductor devices leads to increased parasitic capacitance in dielectric layers between conductive components, which affects the device's performance and reaction speed.
Innovation Solution
The semiconductor device design includes a first conductive via with a specific width and structure, positioned between metal gates, which widens the interval between them, thereby reducing parasitic capacitance. This design involves a first portion with a first width and a base portion with a base width, where the first ratio of the first width to the pitch ranges between 0.2 and 0.7, and the second ratio of the first width to the base width ranges between 0.5 and 0.99.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of semiconductor device is shrunk, then the device scaling is achieved, but the parasitic capacitance of the dielectric layer increases
Solution Approach 1:
The conductive via is designed with non-uniform cross-sectional area along its length, creating different local qualities: a larger base portion for electrical connection and a smaller upper portion for reduced capacitance. This local variation in geometry allows the via to simultaneously provide good electrical connectivity while minimizing parasitic capacitance with adjacent conductive components.
Solution Approach 2:
The patent changes the geometric parameters of the conductive via by varying its cross-sectional area along the vertical direction. Specifically, the via transitions from a larger base width at the bottom to a smaller width at the top, effectively changing the dimensional parameters to reduce the overlapping area with adjacent conductors and thus reduce parasitic capacitance.
2Quantity of substance
If the interval between metal gates is reduced, then the device density is increased, but the parasitic capacitance between conductive components increases
Solution Approach 1:
The conductive via structure employs local quality variation with a tapered or stepped profile, where the upper portion has a smaller cross-sectional area than the base portion. This allows the via to maintain close spacing with adjacent gates for high density while the reduced upper width minimizes the capacitive coupling between the via and neighboring conductive components.
Solution Approach 2:
The patent addresses the two-dimensional spacing constraint by introducing a vertical dimension solution. Instead of increasing horizontal spacing to reduce capacitance, the via's cross-sectional area is varied along the vertical axis, allowing high device density in the planar direction while reducing parasitic capacitance through vertical geometry optimization.
Data Source
AI summary
A semiconductor device includes a substrate, a plurality of oxide definition structures, a plurality of metal gates and a first conductive via. The oxide definition structures are formed on the substrate and arranged in a first direction. The metal gates are formed on the substrate and extend in a second direction. The first conductive via is formed on the substrate, located between two of the metal gates, extends in the first direction and has a first width in the second direction. There is a pitch between adjacent two of the metal gates in the second direction, and a first ratio of the first width to the pitch ranges between 0.2 and 0.7.