Conductive Via Layout for Backside Power Rail Semiconductor Interconnects
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into a given area while maintaining performance, particularly in forming efficient interconnects between transistors and power circuits, leading to issues with parasitic capacitance and resistance.
Innovation Solution
The formation of a semiconductor device with a device layer between front-side and back-side interconnect structures, where conductive vias connect conductive features of the back-side interconnect structure to the front-side interconnect structure, using conductive features instead of semiconductive features to improve performance by reducing resistance and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductive features are used for interconnects, then integration density can be maintained, but resistance and parasitic capacitance increase, degrading performance
Solution Approach 1:
The patent changes the material parameter of the interconnect features from semiconductive to conductive material, fundamentally altering the electrical properties to reduce resistance and parasitic capacitance while maintaining the same interconnect structure and layout
2Productivity
If feature size is reduced to increase integration density, then more components can be integrated, but parasitic effects and manufacturing complexity increase
Solution Approach 1:
By changing the material parameter from semiconductive to conductive, the patent enables smaller feature sizes to be used effectively, as the reduced resistance and parasitic capacitance allow for higher integration density without the performance degradation that would normally occur at smaller dimensions
3Object-generated harmful factors
If conductive features are used instead of semiconductive features, then resistance and parasitic capacitance are reduced, but manufacturing complexity increases
Solution Approach 1:
The conductive interconnect features serve multiple functions: they provide electrical connection between transistors, deliver power to the device layer, and enable high-density integration. This multi-functionality is achieved through the same basic interconnect structure, avoiding the need for separate power delivery mechanisms
Data Source
AI summary
In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.