Conductive Via Layout for Stable Shielding Contact After Singulation
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Solution Overview
Problem
The existing methods for forming conductive vias in semiconductor devices result in reduced contact surface area with shielding layers due to singulation variance, leading to poor ground contact and adhesive integrity, which affects the functionality of shielding layers in high-frequency applications.
Innovation Solution
The use of a staggered or offset pattern for conductive vias during singulation, which maintains a consistent and enhanced contact surface area with the shielding layer, independent of cutting alignment variance, thereby improving adhesion and electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conductive vias are arranged in a linear pattern and singulated, then manufacturing is simplified, but cutting alignment variance reduces the contact surface area with the shielding layer
Solution Approach 1:
The patent transitions from a symmetric linear arrangement of conductive vias to an asymmetric staggered or offset pattern. This asymmetric arrangement ensures that the cumulative contact surface area between the shielding layer and conductive vias remains consistent even when singulation cutting alignment varies, thereby resolving the contradiction between manufacturing simplicity and contact surface area consistency.
2Productivity
If conductive vias are singulated through the substrate panel, then individual packages are formed, but cutting variance causes off-center cuts that reduce exposed side surface area
Solution Approach 1:
The staggered or offset pattern of conductive vias creates an asymmetric distribution that compensates for cutting variance during singulation. This ensures that the cumulative exposed side surface area remains sufficient for reliable adhesive bonding, maintaining reliability while preserving productivity benefits of singulation.
Solution Approach 2:
The patent proactively designs the conductive via arrangement to anticipate and compensate for potential cutting alignment variations. By pre-positioning vias in a staggered pattern, the design creates a buffer that ensures adequate contact surface area is maintained even when cutting variance occurs, preventing adhesive integrity issues before they arise.
3Adaptability or versatility
If conductive vias are cut off-center during singulation, then singulation flexibility is maintained, but the fractional cylinder has reduced vertical surface area for contact
Solution Approach 1:
The patent employs an asymmetric staggered arrangement of conductive vias that is specifically designed to maintain cumulative contact surface area across varying singulation alignments. This asymmetric pattern ensures that as cutting alignment varies, the distribution of exposed surfaces across multiple vias compensates for individual via exposure variations, maintaining adequate total contact area while preserving singulation flexibility.
Data Source
AI summary
A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate in an offset pattern. An electrical component is disposed in a die attach area over a first surface of the substrate. The conductive vias are formed around the die attach area of the substrate. A first conductive layer is formed over the first surface of the substrate, and a second conductive layer is formed over the second surface. An encapsulant is deposited over the substrate and electrical component. The substrate is singulated through the conductive vias. A first conductive via has a greater exposed surface area than a second conductive via. A shielding layer is formed over the electrical component and in contact with a side surface of the conductive vias. The shielding layer may extend over a second surface of substrate opposite the first surface of the substrate.