Conductive Vias with Silicon Insulating Spacers for Deformation Control
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Solution Overview
Problem
The thinning of semiconductor substrates in semiconductor packages increases the risk of deformation and delamination of conductive vias during thermal processing, such as reliability testing and bonding to a package substrate, due to their increased vulnerability.
Innovation Solution
The implementation of insulating spacers, specifically made of silicon-comprising materials like silicon nitride, silicon oxide, or silicon oxynitride, on the sidewalls of conductive vias to enhance their rigidity and provide structural support, reducing the risk of deformation and manufacturing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the substrate is thinned to reduce package size, then the package profile is reduced, but the conductive vias become more vulnerable to deformation and delamination during thermal processing
Solution Approach 1:
The support structure is segmented into multiple insulating layers (first insulating layer, second insulating layer) with a stress buffer layer positioned between them. This segmentation allows each layer to perform specific functions: the first insulating layer provides electrical insulation, the stress buffer layer manages thermal stress, and the second insulating layer provides additional support, collectively preventing via deformation while maintaining a thinned package profile.
Solution Approach 2:
The stress buffer layer acts as an intermediary element positioned between the first and second insulating layers. This intermediary structure absorbs and distributes thermal stress during processing, preventing direct stress transmission to the conductive vias that extend through the substrate, thereby protecting them from deformation and delamination.
2Manufacturing precision
If insulating spacers are added to support conductive vias, then via deformation is reduced, but device complexity increases
Solution Approach 1:
The insulating layers serve multiple functions simultaneously: they provide electrical insulation around the conductive vias, provide mechanical support to prevent deformation, and the stress buffer layer specifically manages thermal stress. This multi-functionality reduces the need for separate dedicated support structures, thereby limiting the increase in device complexity while achieving effective via protection.
Solution Approach 2:
The patent modifies the structural parameters of the package by introducing layered insulating structures with specific material properties. The stress buffer layer is positioned at a specific depth between the insulating layers, and the conductive vias are formed with specific dimensions (5-10 micrometers) to optimize their stability. These parameter changes enable effective deformation control while maintaining manufacturing feasibility.
Data Source
AI summary
An embodiment method includes bonding a first die to a first side of an interposer, the interposer comprising a substrate; after bonding the first die to the first side of the interposer, depositing a first insulating layer on a second side of the interposer opposite the first side; patterning an opening through the substrate and the first insulating layer; and depositing a second insulating layer over the first insulating layer and along sidewalls and a lateral surface of the opening. The second insulating layer comprises silicon. The method further includes removing lateral portions of the second insulating layer to define a sidewall spacer on sidewalls of the opening and forming a through via in the opening, wherein the through via is electrically connected to the first die.