Conductive Via Staircase Bonding in 3D Memory-Logic Stacks
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently integrating three-dimensional memory devices with logic dies, particularly in forming effective electrical connections through conductive via structures in staircase regions.
Innovation Solution
A bonded assembly is formed by integrating a memory die with a logic die, featuring conductive via structures that extend through alternating stacks, including column-shaped conductive via structures with shaft and capital portions, and logic-side metal interconnect structures for electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding methods are used to integrate memory die with logic die, then the bonding process is simple, but electrical connections through conductive via structures in staircase regions are insufficient
Solution Approach 1:
The conductive via structures are segmented into multiple functional portions: a first conductive portion extending through the staircase region, a second conductive portion within the via hole, and a third conductive portion providing the bond pad. This segmentation allows each portion to be optimized for its specific function while collectively providing robust electrical connections.
Solution Approach 2:
The conductive via structures extend in multiple dimensions through the alternating stack, with vertical extension through the staircase region and horizontal positioning within via holes. This multi-dimensional approach enables effective electrical connections through the complex three-dimensional memory structure.
2Reliability
If conductive via structures extend through all layers of the alternating stack, then electrical connectivity is improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The conductive via structures have different properties in different regions: the first conductive portion has properties optimized for extending through the staircase region, the second conductive portion is optimized for filling the via hole, and the third conductive portion is optimized for providing the bond pad. This local optimization enables effective manufacturing while maintaining electrical connectivity.
Solution Approach 2:
The alternating stack is formed with predetermined via holes at specific locations before the conductive via structures are formed. This preliminary preparation of the stack structure with pre-positioned via holes simplifies the subsequent formation of conductive via structures by providing clear guidance for their placement and formation.
3Quantity of substance
If the alternating stack structure is used for three-dimensional memory, then storage density is improved, but forming effective electrical connections through staircase regions becomes difficult
Solution Approach 1:
The first conductive portion acts as an intermediary element that bridges the staircase region and connects the underlying electrically conductive layers. This intermediary structure enables electrical connections through the complex staircase geometry without compromising the three-dimensional memory architecture.
Solution Approach 2:
The conductive via structures are nested within the alternating stack structure, with the via structures positioned within via holes that are formed through the alternating layers. This nesting approach allows electrical connections to be integrated within the three-dimensional memory structure without disrupting the high-density architecture.
Data Source
AI summary
A bonded assembly includes first memory die bonded to a logic die. The first memory die includes a first alternating stack of first insulating layers and first electrically conductive layers, first memory openings vertically extending through the first alternating stack, first memory opening fill structures located within the first memory openings and containing a respective vertical stack of first memory elements and a respective vertical semiconductor channel, electrically conductive first side-contact via structures vertically extending through each layer within the first alternating stack and contacting a sidewall of a respective one of the first electrically conductive layers, and first memory-side bonding pads. The logic die includes a peripheral circuitry configured to control operation of the first memory die, logic-side metal interconnect structures, and logic-side bonding pads that are bonded to the first memory-side bonding pads.


