Conductive Via Pad Structure for Bonding Stress Distribution
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues with bonding stress concentration and reliability of electrical connections.
Innovation Solution
The formation of multiple conductive via structures between a conductive pad and a conductive line, which share bonding stress and provide additional support, reducing the risk of passivation layer cracking and delamination, and improving the reliability of electrical connections by increasing the connection area and reducing electromigration effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process difficulty increases and reliability of electrical connections deteriorates
Solution Approach 1:
The patent divides a single conductive connection into multiple conductive via structures (first conductive via structure and second conductive via structure) that connect the conductive pad to the conductive line. This segmentation distributes the bonding stress across multiple connection points, improving reliability while maintaining the scaled-down feature sizes needed for high productivity.
2Productivity
If feature sizes are decreased to increase functional density, then more circuits per chip area are achieved, but fabrication process complexity increases
Solution Approach 1:
The conductive connection is segmented into multiple via structures with different cross-sectional areas. The first conductive via structure has a larger cross-sectional area than the second, allowing differential stress distribution. This segmented approach manages fabrication complexity by creating a structured, multi-layer connection system that can be systematically manufactured.
Solution Approach 2:
Different portions of the conductive connection structure have different cross-sectional areas tailored to local requirements. The first conductive via structure has a larger cross-section where stress concentration occurs, while the second has a smaller cross-section. This local quality variation optimizes stress distribution without uniformly increasing the complexity of the entire structure.
3Ease of manufacture
If bonding stress is concentrated in a single conductive via structure, then manufacturing is simpler, but the risk of passivation layer cracking and delamination increases
Solution Approach 1:
The single conductive via is segmented into multiple conductive via structures (first and second conductive via structures) that share the bonding stress. This segmentation prevents stress concentration that would cause passivation layer cracking and delamination, while still being manufacturable using standard multi-patterning techniques.
Solution Approach 2:
The structure is designed with a first conductive via structure having a larger cross-sectional area than the second, creating a stress-distributing configuration beforehand. This preemptive design cushions against bonding stress concentration, preventing passivation layer failure before it occurs during the bonding process.
Data Source
AI summary
A chip structure is provided. The chip structure includes a substrate. The chip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.


