Conductive Via Formation on Thinned Wafers

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Solution Overview

Problem

The fabrication of through silicon via (TSV) on thinned wafers with bonded carrier wafers is challenging due to thermal limitations of bonding materials, and existing methods avoid metal etching within the drilling process, which can complicate the formation of reliable electrical connections.

Innovation Solution

A method involving etching a cavity through an electrically conductive pad, forming dielectric liner layers, and depositing a conductive material to create a via with different diameter portions, allowing for a conductive via extending through the substrate while minimizing handling issues and thermal challenges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If TSV via last from back (VLFB) fabrication method is used on thinned wafer with bonded carrier wafer, then through silicon via can be formed, but thermal limitation of bonding material restricts the processing temperature and complicates fabrication

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidbonding material thermal limit

Core Design Contradiction:

ReliabilityVSTemperature

Solution Approach 1:

The patent inverts the conventional VLFB approach by performing via formation from the front surface instead of the back surface. This allows the via to be formed through the substrate thickness without being constrained by the thermal limitations of bonding materials on the back side, enabling higher temperature processing and more reliable electrical connections.

Inventive Principle:

Principle #13The other way round (Inversion)

2Ease of manufacture

If conventional via formation methods are used that avoid metal etching, then bonding material thermal limitations are respected, but the formation of reliable electrical connections becomes complicated

Engineering Contradiction:

Improvevia formation process simplicityVSAvoidelectrical connection reliability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a cavity through the substrate before depositing the conductive material. This pre-formed cavity provides a defined pathway for the conductive via, ensuring reliable electrical connection while simplifying the overall manufacturing process by separating the etching and deposition steps.

Inventive Principle:

Principle #10Preliminary action

3Manufacturing precision

If multiple dielectric layers are etched in conventional TSV VLFT approach, then via can be formed, but metal and active dummy layers must be excluded within TSV design area adding complexity

Engineering Contradiction:

Improvevia formation precisionVSAvoidTSV design area complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the via formation process into distinct steps: forming a cavity through the substrate, depositing dielectric liner layers on the cavity walls, and filling with conductive material. This segmentation allows each step to be optimized independently, achieving high manufacturing precision without requiring exclusion of metal and active dummy layers from the TSV design area.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of reliable electrical connections with reduced handling issues and thermal challenges, improving the fabrication of TSVs on thinned wafers and allowing for more efficient processing of 3D devices.

Implementation Method 1

forming a cavity on a front surface of a substrate, the substrate including an electrically conductive pad, by etching through the electrically conductive pad

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

depositing a suitable electrically conductive material into the cavity and the via hole to form a conductive via

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS11508619B2Electrical connection structure and method of forming the same

Publication Date: 2022.11.22 AGENCY FOR SCI TECH & RES

AI summary

Various embodiments may provide a method of forming an electrical connection structure. The method may include forming a cavity on a front surface of a substrate, the substrate including an electrically conductive pad, by etching through the electrically conductive pad. The method may also include forming one or more dielectric liner layers covering an inner surface of the cavity. The method may further include forming a via hole extending from the cavity by etching through the one or more dielectric liner layers, forming one or more further dielectric liner layers covering an inner surface of the via hole. The method may additionally include depositing a suitable electrically conductive material into the cavity and the via hole to form a conductive via having a first portion in the cavity and a second portion in the via hole, a diameter of the first portion different from a diameter of the second portion.