Conductive Vias in Semiconductor Package Signal Routing
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Solution Overview
Problem
Current package-on-package semiconductor device packaging methods face challenges with increased signal travel distance, higher resistance, lower speed, and higher costs due to larger substrate sizes and complex routing, which restricts their ability to meet next-generation requirements for reduced memory interface pitches, higher integration, and smaller package thickness.
Innovation Solution
The use of conductive vias that intersect wire bonds within the package substrate to provide direct electrical connections, reducing signal travel distance and substrate complexity by avoiding the need for built-up interconnects, and utilizing through vias and blind vias to establish connectivity within the package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional package-on-package methods with built-up interconnects are used, then electrical connections between devices are established, but signal travel distance increases and resistance increases
Solution Approach 1:
The patent transitions from planar substrate routing to three-dimensional vertical routing by drilling conductive vias through the molding compound. This dimensional change allows signals to travel directly vertically from wire bonds through the via to the substrate, eliminating the need for long horizontal paths across the substrate surface and significantly reducing signal travel distance.
Solution Approach 2:
The patent combines multiple functions into the conductive via structure: it serves as both the electrical connection path and the signal routing mechanism. By merging the via fill material with conductive properties, the patent eliminates the need for separate interconnect layers and substrate routing, thereby reducing both signal travel distance and resistance.
2Productivity
If through mold vias and through silicon vias are used to increase connections, then connection density increases, but substrate size and manufacturing complexity increase
Solution Approach 1:
The patent extracts the interconnect function from the substrate and relocates it to the molding compound via conductive vias. This extraction allows the substrate to remain simple while achieving high connection density through the via structure, thereby reducing substrate design and manufacturing complexity.
Solution Approach 2:
The patent changes the physical and electrical parameters of the molding compound by incorporating conductive fill material into the vias. This parameter change enables the molding compound to provide both mechanical protection and electrical connectivity, increasing connection density without complicating the substrate.
3Reliability
If wire bond device package is used, then device connections are established, but routing distance is long resulting in increased resistance and lower speed
Solution Approach 1:
The patent introduces vertical three-dimensional routing through conductive vias, replacing the traditional horizontal planar routing path. This dimensional change creates a direct vertical signal path from the wire bond through the via to the substrate contact, dramatically reducing routing distance and increasing signal propagation speed.
Solution Approach 2:
The conductive via fill material acts as an intermediary that provides a low-resistance electrical path between the wire bond and the substrate. This intermediary structure replaces the high-resistance long horizontal path through the substrate, thereby reducing resistance and increasing signal speed.
4Productivity
If larger substrate size is used to accommodate complex routing, then more connections can be made, but package size and cost increase
Solution Approach 1:
The patent moves the routing function from the two-dimensional substrate plane to the three-dimensional vertical space through conductive vias. This allows multiple connections to be established through vertical via paths rather than requiring expanded substrate area, thereby increasing connection capacity without increasing package size.
Solution Approach 2:
The patent changes the electrical conductivity parameter of the molding compound by adding conductive fill material to the vias. This parameter change enables the molding compound to serve as the routing medium, allowing high connection density to be achieved through the via structure rather than through substrate expansion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces signal propagation time, decreases substrate size and complexity, and lowers manufacturing costs by enabling more efficient signal routing and package stacking configurations, while minimizing warpage issues and allowing for smaller, more integrated device designs.
Implementation Method 1
The conductive via is formed to be in electrical contact with the severed ends of the severed wire bond and the conductive via electrically couples the contact surface with the severed ends of the severed wire bond
Data Source
AI summary
A mechanism is provided by which signal travel distance within and between semiconductor device packages is reduced and substrate size and complexity can be reduced. This capacity is provided by virtue of a conductive via that intersects a wire bond molded within a package substrate. The via provides a direct electrical connection between an external signal transmitter or receiver and the points connected by the wire bond, and thereby avoiding the need for the signal to transit built up interconnects in the semiconductor device package. Conductive vias can provide connectivity through or to a package substrate, and can be through vias or blind vias. The conductive via is formed by either mechanical or laser drilling, and is filled using standard fill techniques, and is therefore readily incorporated into a package production flow.