Semiconductor Conductor Lines Overlapping Contact Pads

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Solution Overview

Problem

Current wafer level packaging technologies face limitations in routing density due to design constraints, necessitating advancements in conductor line distribution and external contact pad configurations to enhance packaging efficiency.

Innovation Solution

The implementation of a method involving multiple metallization layers and the strategic placement of external contact pads overlapping conductor lines, allowing for increased routing density by extending the redistribution layer beyond the semiconductor chip outline through the use of electrically insulating materials and advanced manufacturing processes such as galvanic deposition and lamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conductor lines are routed within the semiconductor chip outline, then manufacturing is simpler, but routing density is limited

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidrouting density
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

The patent extends conductor lines from the traditional planar routing within the chip outline into the third dimension by allowing them to protrude beyond the chip outline and be embedded in the substrate. This dimensional extension enables additional routing paths that were previously unavailable, thereby increasing routing density without complicating the manufacturing process

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If external contact pads are placed far apart, then manufacturing is easier, but package area increases

Engineering Contradiction:
Improvemanufacturing easeVSAvoidpackage area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent embeds the protruding conductor lines and external contact pads within the substrate, creating a nested structure where the redistribution layer is contained within the substrate volume. This nesting allows contact pads to be positioned closer together while maintaining manufacturing feasibility, thereby reducing the overall package area

Inventive Principle:
Principle #7Nested doll (Nesting)

3Quantity of substance

If conductor lines are extended beyond chip outline, then routing density increases, but manufacturing complexity increases

Engineering Contradiction:
Improverouting densityVSAvoidmanufacturing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent forms the protruding conductor lines and external contact pads as part of the redistribution layer before substrate mounting. This preliminary formation of the extended conductor structure allows subsequent substrate embedding and contact pad placement to proceed using standard manufacturing processes, thereby increasing routing density without proportionally increasing manufacturing complexity

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach increases routing density, enabling more efficient packaging with relaxed constraints on pad size and pitch, thereby facilitating improved second-level assembly and reducing production costs while maintaining compact package dimensions.

Implementation Method 1

advanced manufacturing processes such as galvanic deposition and lamination

Methodology Applied
Scientific EffectGalvanic deposition: Electrodeposition

Implementation Method 2

advanced manufacturing processes such as galvanic deposition and lamination

Methodology Applied
Scientific EffectLamination: Lamination

Data Source

PatentUS8080880B2Semiconductor device with arrangement of parallel conductor lines being insulated, between and orthogonal to external contact pads
Publication Date: 2011.12.20 INTEL CORP
  • US8080880B2 patent drawing
  • US8080880B2 patent drawing
  • US8080880B2 patent drawing

AI summary

A semiconductor device and manufacturing method. One embodiment provides a device including a semiconductor chip. A first conductor line is placed over the semiconductor chip. An external contact pad is placed over the first conductor line. At least a portion of the first conductor line lies within a projection of the external contact pad on the semiconductor chip.