Semiconductor Conductor Patterning With Selective Etch Caps
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing down-scaling of integrated circuits exacerbates optical proximity effects, making it challenging to maintain resolution and design rule compliance when features are close together, particularly in photolithography processes.
Innovation Solution
The solution involves capping parallel conductors with caps of different etch sensitivities, allowing for the selective removal of selected portions without violating layout design rules, thereby overcoming the need for dummy pitches or additional etching steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If photolithography is used to expose photo resist for forming closely spaced features, then feature density is improved, but optical proximity effects occur causing line width variations and process control issues
Solution Approach 1:
The patent divides the pattern formation into multiple discrete etching steps (first cut, second cut, third cut) with different selectivities. Each step selectively removes material based on cap structure differences, allowing precise control of line widths and spaces that would be impossible to achieve with single-step photolithography alone.
Solution Approach 2:
Different cap structures with varying etch selectivities are applied to specific regions of the conductors. The first caps have different selectivity than the second caps, enabling localized differentiation during etching steps. This allows certain conductor portions to be selectively removed while preserving others, achieving precise pattern control.
2Area of stationary object
If features are placed closer together to increase density, then area utilization is improved, but the space between features becomes beyond the resolution limit of the light source
Solution Approach 1:
The patent introduces a vertical dimension by forming cap structures of different heights and materials over the conductors. This third dimension (height/depth) provides an additional degree of freedom for pattern definition, allowing features to be placed closer horizontally while still being distinguishable through their vertical cap structures during selective etching.
Solution Approach 2:
Cap structures are formed on the conductors before the pattern transfer step. These pre-formed caps with different etch selectivities serve as protective masks that guide subsequent etching steps, enabling precise pattern formation at densities beyond the photolithography resolution limit.
3Manufacturing precision
If dummy pitches or additional etching steps are used to maintain design rules, then design rule compliance is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The cap structures serve multiple functions simultaneously: they act as protective masks during selective etching, define pattern boundaries, and enable design rule compliance. The first and second caps work together across multiple etching steps to control both conductor removal and spacing, eliminating the need for separate dummy pitch structures.
Solution Approach 2:
The patent utilizes changes in etch selectivity parameters between different cap materials and different etching steps. By adjusting selectivity ratios (e.g., first cut selectivity between first cap and second cap, second cut selectivity between second cap and third cap), the process achieves precise pattern control with fewer steps than conventional methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the combination of layouts with minimal width and height separations, maintaining design rule compliance while reducing the number of etching steps required, thus improving manufacturing efficiency and precision.
Implementation Method 1
capping parallel conductors with caps of different etch sensitivities, allowing for the selective removal of selected portions
Data Source
AI summary
A method (of manufacturing conductors for a semiconductor device) includes: forming active regions (ARs) in a first layer, the ARs extending in a first direction; forming a conductive layer over the first layer; forming first, second and third caps over the conductive layer, the caps extending in a second direction perpendicular to the first direction, and the caps having corresponding first, second and third sensitivities that are different from each other; removing portions of the conductive layer not under the first, second or third caps resulting in gate electrodes under the first caps and first and second drain/source (D/S) electrodes correspondingly under the second or third caps; and selectively removing portions of corresponding ones of the first D/S electrodes and the second D/S electrodes.