Conductor Pillars in 3D NAND Memory for Low Resistance Power Distribution
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Solution Overview
Problem
In three-dimensionally stacked flash memory devices, the conductive portions other than the uppermost interconnect layer face challenges in rapidly achieving desired potentials due to increased resistance as the device size grows, leading to longer data write, read, and erase times and potential malfunctions, and dividing memory cell arrays increases chip area.
Innovation Solution
A nonvolatile semiconductor memory device with a substrate, alternately stacked dielectric and electrode films, conductor pillars with lower resistivity than semiconductor pillars, and a shunt interconnect connected to the conductor pillars, allowing for efficient potential application across the cell source, reducing the need for multiple memory cell arrays and peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the area of the stacked flash memory is increased to increase the capacity, then the memory capacity is improved, but the resistance of the conductive portions increases
Solution Approach 1:
The patent introduces a new vertical dimension for power supply by forming conductor pillars that extend from the upper surface through the stacked body to the lower surface. This third-dimensional conductive path allows electrical potential to be supplied from both upper and lower directions simultaneously, resolving the resistance increase problem when device area is expanded for higher capacity.
Solution Approach 2:
The conductive portion is segmented into multiple independent paths: conductor pillars extending vertically through the stack, upper electrode films, and lower electrode films. This segmentation creates parallel current paths that reduce overall resistance, allowing the device to maintain low resistance even as the memory array area increases for higher capacity.
2Quantity of substance
If the area of the stacked flash memory is increased to increase the capacity, then the memory capacity is improved, but the time required for data write, read, and erase operation increases
Solution Approach 1:
By adding vertical conductor pillars that penetrate the stacked body, the patent creates a three-dimensional power distribution network. This allows simultaneous potential application from upper and lower electrodes, dramatically reducing the time constant for charging/discharging the cell source region, thus decreasing operation time even as device area increases for higher capacity.
Solution Approach 2:
The conductor pillars are pre-formed to establish low-resistance vertical conductive paths before the memory cells are fully assembled. This preliminary establishment of efficient current paths ensures that when data operations occur, the electrical potential can be rapidly applied throughout the expanded device area, reducing operation time.
3Reliability
If division into a plurality of memory cell arrays is implemented to avoid upsizing of conductive portions, then the resistance is reduced, but the chip area increases
Solution Approach 1:
Instead of dividing the memory into multiple planar arrays (which increases chip area), the patent uses vertical conductor pillars to create a three-dimensional power distribution system. This allows a single large memory cell array to maintain low resistance by receiving power from both upper and lower directions simultaneously, achieving low resistance without increasing chip area through division.
Solution Approach 2:
The patent merges the power supply function into the vertical stack structure itself by forming conductor pillars that integrate with the stacked body. This combines the memory cell array and power distribution into a unified three-dimensional structure, eliminating the need for separate divided arrays and their associated peripheral circuits, thus reducing chip area while maintaining low resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables rapid charging and potential adjustment of the cell source, reducing operation times and avoiding malfunctions, while allowing for larger device sizes without increasing chip area by eliminating the need for multiple memory cell arrays and peripheral circuits.
Implementation Method 1
conductor pillars buried inside a subset of the plurality of through holes, the conductor pillar having a lower resistivity than the semiconductor pillar
Data Source
AI summary
In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.