Predicting Tolerable Conductor Spacing via Statistical Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for predicting tolerable spacing between conductors in semiconductor devices are inefficient and subjective, relying on intuitive visual analysis and extensive manual inspection, leading to inconsistent results and increased production time, especially as semiconductor sizes shrink and alignment accuracy becomes critical.
Innovation Solution
A statistical method using dedicated hardware or software to predict tolerable spacing by forming testing conductors with varied deviations, analyzing failure counts, and determining standard deviations to establish a systematic and scalable approach for determining optimal conductor spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conductor spacing is reduced to shrink semiconductor device size, then device integration density is improved, but alignment accuracy deteriorates leading to shorts between conductors
Solution Approach 1:
The patent applies preliminary action by performing multiple lithography processes with intentional deviations before final conductor formation. Testing conductors are formed with predetermined deviations from the target position, allowing the system to pre-characterize alignment variations and establish safe spacing margins before actual device production, thus preventing shorts while maximizing density
Solution Approach 2:
The patent changes parameters by systematically varying the spacing between testing conductors and introducing controlled deviations in lithography alignment. By measuring failure counts across different spacing parameters and deviation magnitudes, the method determines optimal spacing values that maintain reliability while minimizing device area
2Measurement precision
If extensive manual inspection is performed to determine tolerable spacing, then measurement precision is improved, but productivity deteriorates due to time-consuming inspection processes
Solution Approach 1:
The patent segments the inspection process by focusing examination on specific testing conductor regions with known deviations rather than inspecting entire semiconductor wafers. By dividing the problem into discrete spacing scenarios (different deviations, different spacing values), the method achieves precise spacing predictions while examining only representative samples
Solution Approach 2:
The patent uses copying by creating testing conductors that replicate actual conductor geometries and materials but with intentional spacing variations. These test structures serve as proxies for real devices, allowing precise measurement of alignment tolerances without requiring exhaustive inspection of production devices
3Ease of operation
If visual analysis by operators is used to determine safe window, then ease of operation is improved, but manufacturing precision deteriorates due to subjective judgment variations
Solution Approach 1:
The patent replaces the mechanical/visual analysis system with an automated electrical measurement system. Instead of operators visually examining conductor alignment, the method uses electrical tests (such as capacitance measurements or continuity tests) to objectively detect shorts between conductors, eliminating subjective judgment and providing consistent, quantifiable data for spacing determination
Data Source
AI summary
A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+Δd to d−Δd wherein d is the standard spacing and Δd<d. Then, the wafer is inspected to find failure counts corresponding to each contact-to-gate distance. The tolerable spacing is determined according to the failure counts and the contact-to-gate distances based on a statistical method.