Conductor Subdivision for Parasitic Extraction Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the process of parasitic extraction for integrated circuit design, existing technologies face a trade-off between accuracy and efficiency due to the need for detailed process information from foundries, which can make the layout-versus-schematic (LVS) process time-consuming and resource-intensive.
Innovation Solution
A computing system performs a layout-to-schematic process and parasitic extraction by subdividing conductors in the device-level layout design based on conversion rules corresponding to physical properties described in a technology file, generating a physical layout design and extracting electrical representations to form a netlist, thereby aligning the granularity of layers and connectivity for more accurate parasitic extraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If detailed process information from foundries is used for parasitic extraction, then accuracy of parasitic extraction is improved, but the LVS process becomes time-consuming and resource-intensive
Solution Approach 1:
The patent segments the conductor geometry into multiple portions based on different layer granularities. A first portion is extracted using detailed foundry process information for high accuracy, while a second portion is extracted using simplified geometric data for speed. This segmentation allows the system to balance accuracy and efficiency by applying different extraction methodologies to different parts of the same conductor structure.
2Measurement precision
If detailed process information from foundries is used for parasitic extraction, then accuracy of parasitic extraction is improved, but computational resources are consumed excessively
Solution Approach 1:
The patent segments the conductor geometry into multiple portions based on different layer granularities. A first portion is extracted using detailed foundry process information for high accuracy, while a second portion is extracted using simplified geometric data for speed. This segmentation allows the system to balance accuracy and efficiency by applying different extraction methodologies to different parts of the same conductor structure.
3Productivity
If conductor geometry is extracted at a single granularity level, then processing efficiency is maintained, but accuracy of parasitic extraction is compromised
Solution Approach 1:
The patent applies local quality by extracting different portions of conductor geometry at different granularity levels appropriate to their specific contexts. Critical regions requiring high precision are extracted with detailed foundry process information, while less critical regions use simplified geometric data. This local differentiation optimizes both accuracy and efficiency by matching extraction detail to actual need.
Data Source
AI summary
A computing system can perform a layout-to-schematic process on a geometric layout design of an integrated circuit, which can generate a device-level layout design for the integrated circuit. The computing system also can perform a parasitic extraction process on the geometric layout design by utilizing the device-level layout design for the integrated circuit. The computing system implementing the parasitic extraction process can sub-divide a conductor in the device-level layout design into multiple sub-divided conductor portions based on conversion rules corresponding to the physical properties of layers for the integrated circuit described in a technology file. The computing system can generate a physical layout design of the integrated circuit from the device-level layout design having the sub-divided conductor portions based on the technology file. The computing system can extract electrical representations of nets corresponding to the conductors in the physical layout design to form a netlist for the physical layout design.