Confidential-Bit Processing Circuit for Fault Attack Detection
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Solution Overview
Problem
Existing information processing devices face challenges in effectively counteracting fault attacks (FA) that target confidential information by physically stimulating the device to induce miscalculations, particularly with methods like Safe Error Attack and Exponent Blinding being insufficient or complex.
Innovation Solution
The proposed solution involves an information processing device with a calculation circuit comprising a first and second calculation circuit, a control circuit, a counter circuit, and a comparison circuit. The device processes bits of confidential information, executing different calculations based on the bit's logic value, and uses a counter to detect faults by comparing the expected counter value with the actual counter value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Exponent Blinding is used to conceal confidential information with a random number, then security against fault attacks is improved, but processing complexity increases due to random number generation and encryption
Solution Approach 1:
The invention extracts and monitors the execution path by counting the number of times the second calculation circuit is invoked. This counter value serves as a simplified indicator of confidential information processing, allowing fault detection without requiring complex random number generation or encryption operations. The counter extraction replaces the complex Exponent Blinding mechanism with a lightweight monitoring approach.
Solution Approach 2:
The invention implements feedback by comparing the actual counter value (obtained during execution) with an expected counter value (pre-calculated based on confidential information). This feedback mechanism enables real-time detection of fault attacks without adding processing complexity, as the comparison simply verifies whether the execution path matches the expected behavior.
2Measurement precision
If Safe Error Attack countermeasures are implemented, then detection capability is improved, but the method fails to prevent stealing of confidential information
Solution Approach 1:
The invention uses feedback comparison between actual and expected counter values to not only detect faults but also protect confidential information. When the counter values disagree, it indicates a fault attack has occurred, and the system can respond by discarding the compromised calculation result. This feedback loop provides both detection and protection capabilities.
Solution Approach 2:
The invention performs preliminary anti-action by pre-calculating the expected counter value based on the confidential information before execution begins. This pre-computed expectation serves as a reference for detecting any deviations caused by fault attacks, enabling the system to take preventive measures against information theft before the attack can succeed.
3Measurement precision
If detailed error detection codes are calculated and stored for each bit, then fault detection precision is improved, but device complexity and processing overhead increase
Solution Approach 1:
The invention merges the fault detection function into the existing calculation structure by using the invocation count of the second calculation circuit as the detection parameter. Instead of adding separate error detection circuits for each bit, the counter consolidates the detection function across all operations, maintaining high detection precision while avoiding increased device complexity.
Solution Approach 2:
The counter circuit serves multiple functions: it tracks execution flow, detects fault attacks, and provides input for the comparison circuit. This multi-functional design eliminates the need for separate dedicated error detection hardware for each bit operation, reducing overall device complexity while maintaining comprehensive monitoring capability.
Data Source
AI summary
A control circuit executes; processing a plurality of bits constituting confidential information one after another, each of the bits being a processing target bit; causing a calculation circuit to execute a first calculation by a first calculation circuit and a second calculation by a second calculation circuit when the processing target bit has a logic value of “1”; and causing the calculation circuit to execute only the second calculation of the first calculation and the second calculation when the processing target bit has a value of “0”. A counter circuit outputs a counter value based on the number of processing target bits subjected to only the second calculation of the first calculation and the second calculation by the calculation circuit. A comparison circuit compares the counter value with an expected value for the counter value based on the confidential information.