Confidential FPGA Code Verification via Trusted Execution Environment
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Solution Overview
Problem
Current FPGA implementations lack isolation between codes from different users, leading to potential interference and security risks, such as permanent denial of service (pDOS) and intellectual property exposure, which hinders the adoption of FPGA cloud services due to vulnerabilities in malicious or buggy code and the need to protect sensitive user data.
Innovation Solution
A trusted execution environment (TEE) is established to encrypt and integrity protect FPGA code using a policy-defined framework, ensuring confidentiality and integrity through secure attestation and authentication, allowing only compliant code to be loaded onto the FPGA while maintaining user control over code exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FPGA code from different users is allowed to run without isolation, then resource utilization and service efficiency are improved, but security risks and intellectual property exposure increase
Solution Approach 1:
The patent segments the FPGA configuration process into separate encrypted code streams, each protected with unique encryption keys. Multiple users' code is divided into isolated configuration segments that are individually encrypted and authenticated, preventing interference and security breaches while allowing concurrent execution on the same FPGA device.
Solution Approach 2:
The patent introduces a trusted execution environment (TEE) as an intermediary between code upload and FPGA configuration. The TEE performs confidential verification, encryption, and authentication of code before it reaches the FPGA, acting as a security mediator that enables multi-tenant usage while preventing pDOS attacks and IP exposure.
2Reliability
If code verification and security checks are performed, then security and reliability are improved, but processing time and system complexity increase
Solution Approach 1:
The patent performs code encryption and authentication in advance during the code upload phase, before the code is loaded onto the FPGA. The trusted execution environment completes all security verification, signing, and integrity protection beforehand, so that the FPGA itself only needs to perform simple verification of authentication tags, significantly reducing on-device complexity.
Solution Approach 2:
The patent creates authenticated copies of the original code with attached authentication tags and encryption. Instead of modifying the FPGA hardware to perform complex verification, the system generates verified copies of the code that contain built-in security metadata, allowing simple verification processes while maintaining high reliability.
3Loss of information
If encryption and integrity protection are applied to FPGA code, then confidentiality and integrity are improved, but processing overhead and energy consumption increase
Solution Approach 1:
The patent performs the computationally intensive encryption and integrity protection operations in advance during code upload, before the code is deployed to the FPGA. The trusted execution environment completes all heavy cryptographic processing beforehand, so that the FPGA only needs to perform lightweight verification of authentication tags during configuration, significantly reducing on-device energy consumption and processing overhead.
Data Source
AI summary
The present disclosure provides confidential verification for FPGA code. Confidential verification for FPGA code can include receiving the policy from a cloud service provider (CSP) computing device, wherein the policy comprises a plurality of policy requirements used to determine whether to configure the FPGA using the code, receiving the code and the code encryption key from the user computing device, determining whether the code fulfills the plurality of policy requirements, and when the code fulfills the plurality of policy requirements encrypting and integrity protect the code using the code encryption key and providing the encrypted and integrity protected code to an accelerator loader to configure the FPGA using the code.