Configuration Circuit for Variable Address Packet Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing communication protocols face inefficiencies due to complex multiplexing logic required for varying address lengths, leading to changes in payload and error checking bit positions, which complicates data packet processing in ultra-low power communication systems.
Innovation Solution
The proposed solution involves modifying data packet formats where additional bits are added at the end, maintaining the same bit positions for shorter formats and shifting input positions for longer formats, using shift registers and multiplexers to efficiently process variable address sizes without complex FIFO control logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If complex multiplexing logic is used to handle varying address lengths, then adaptability to different address sizes is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent changes the parameter of address field length to be variable rather than fixed. By allowing the address field length to vary (e.g., from 8 to 32 bits) while maintaining a fixed total packet structure, the system achieves adaptability to different addressing needs without requiring complex multiplexing logic to reposition payload and error checking bits.
Solution Approach 2:
The data packet is segmented into distinct fields with fixed relative positions: address field, data field, and error checking field. This segmentation allows each field to maintain its functional independence while the address field length can vary, eliminating the need for complex multiplexing to rearrange packet components.
2Adaptability or versatility
If complex multiplexing logic is used to handle varying address lengths, then adaptability to different address sizes is improved, but power consumption increases
Solution Approach 1:
The patent changes the parameter of address field length to be variable rather than fixed. By allowing the address field length to vary (e.g., from 8 to 32 bits) while maintaining a fixed total packet structure, the system achieves adaptability to different addressing needs without requiring complex multiplexing to reposition payload and error checking bits.
Solution Approach 2:
The patent uses a simple, fixed-structure packet format that can be processed with minimal logic. Instead of implementing complex, power-intensive multiplexing circuits that dynamically reposition fields, the system uses a straightforward parsing approach where the receiver reads fields in their fixed relative positions, significantly reducing power consumption.
3Speed
If fixed data packet format is used, then processing speed is improved, but adaptability to varying address lengths deteriorates
Solution Approach 1:
The patent changes the parameter of address field length to be variable rather than fixed. By allowing the address field length to vary (e.g., from 8 to 32 bits) while maintaining a fixed total packet structure, the system achieves adaptability to different addressing needs without requiring complex multiplexing to reposition payload and error checking bits.
Solution Approach 2:
The data packet is segmented into distinct fields with fixed relative positions: address field, data field, and error checking field. This segmentation allows each field to maintain its functional independence while the address field length can vary, eliminating the need for complex multiplexing to rearrange packet components.
Data Source
AI summary
A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.


