Configuration Memory Readback Using Encrypted Hash Digests
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Solution Overview
Problem
The verification of configuration memory state in programmable logic devices (PLDs) is cumbersome and insecure, particularly due to the need for authorized access and the time-consuming nature of reading back plaintext configuration data, which can expose proprietary information and introduce security risks.
Innovation Solution
Implementing a silicon interposer-based system with cryptographic hashing and encryption of message digests using SHA3 and AES-GCM, allowing secure and efficient readback of encrypted digests instead of plaintext data, reducing data transfer volume and enhancing security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If readback is enabled for authorized persons to verify configuration memory, then verification capability is improved, but security risk increases due to exposure of proprietary information
Solution Approach 1:
The patent introduces an intermediary verification mechanism using message digests and encryption. Instead of directly exposing configuration data, the system computes a hash digest of the configuration memory and encrypts it with a key shared between the PLD and verification system. This intermediary approach allows verification while preventing direct exposure of proprietary configuration information.
Solution Approach 2:
The patent creates a cryptographic copy (message digest) of the configuration data rather than exposing the original. The hash digest serves as a verified copy that can be transmitted and compared without revealing the actual configuration bits, thus maintaining security while enabling verification.
2Object-affected harmful factors
If readback is disabled to avoid exposure of proprietary information, then security is improved, but verification becomes cumbersome and inaccessible to authorized users
Solution Approach 1:
The encrypted message digest acts as an intermediary that bridges security and accessibility. Authorized users can verify configuration memory by receiving the encrypted digest through the interposer, decrypting it with the shared key, and comparing it to the golden bitstream. This maintains security while making verification accessible to authorized persons.
3Ease of operation
If plaintext configuration data is read back for verification, then verification is straightforward, but transfer time increases and data volume is large
Solution Approach 1:
The patent extracts only the essential verification information (message digest) from the large configuration data set, rather than transferring the entire plaintext configuration. The hash digest captures the integrity information needed for verification in a compact form, dramatically reducing transfer time and data volume while maintaining verification capability.
Solution Approach 2:
The patent changes the parameter representation from full plaintext configuration data to a compressed hash digest. This parameter transformation reduces data size from megabits to a fixed 256-bit (or similar) digest, enabling rapid verification without transferring large amounts of data.
4Reliability
If entire configuration memory is read back, then complete verification is achieved, but processing complexity and time increase for large memories
Solution Approach 1:
The patent merges the verification function into a single cryptographic operation (hashing) that processes the entire configuration memory in one pass. Instead of implementing complex verification logic that reads and compares individual bits, the system uses a unified hash function that inherently processes all data and produces a single verification result, simplifying the overall processing architecture.
Data Source
AI summary
Multiple semiconductor dice are disposed on a silicon interposer and are communicatively coupled via the interposer. A first die includes a first memory and a readback circuit, which is coupled to the first memory and coupled to receive a readback command communicated through the interposer. A hash circuit on the first die is configured to generate a message digest from data in the first memory, and an encryption circuit on the first die is configured to encrypt the message digest into an encrypted message digest. The encrypted message digest is accessible through the interposer.