Reconfigurable Processor Configuration Memory Mapping for Loop Parallelism
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Reconfigurable processors face inefficiencies in processing tasks with changed work contents due to fixed hardware functions, and software processing is slower than hardware processing, necessitating an optimization of configuration memory usage.
Innovation Solution
A method and apparatus that analyze parallelism in program code loops, schedule function units, and generate configuration data for efficient mapping in a configuration memory with varying field sizes, using irregular encoding and buffering to optimize memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If configuration memory is optimized by sequential mapping with irregular encoding, then memory usage efficiency is improved, but mapping complexity increases
Solution Approach 1:
The configuration memory is divided into multiple fields with different sizes, where each field can store configuration data for specific function units. This segmentation allows efficient packing of variable-length configuration data into fixed memory structures, reducing overall memory usage while managing complexity through structured organization.
Solution Approach 2:
Different fields in the configuration memory are allocated with different sizes based on the specific requirements of function units. This local quality approach ensures that each field has just enough space for its intended purpose, avoiding wasted memory while the systematic field structure keeps mapping complexity manageable.
2Productivity
If function units are scheduled and activated based on loop parallelism analysis, then processing speed is improved, but scheduling complexity increases
Solution Approach 1:
The system performs preliminary analysis of loop parallelism in program code and pre-schedules function unit activations before execution. This preliminary action identifies parallel execution opportunities in advance, enabling the reconfigurable processor to activate appropriate function units in optimal sequences, thereby improving processing speed while the analysis framework manages scheduling complexity.
Solution Approach 2:
The function unit scheduling system dynamically adapts activation sequences based on the analyzed parallelism characteristics of different loops. This dynamic approach allows the system to optimize processing speed for each specific loop structure while the underlying analysis methodology provides a systematic way to handle the varying scheduling requirements.
Data Source
AI summary
A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.