Configurable 3D Memory Merging Peripheral Logic Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 3D stacked memory devices face challenges in balancing performance and power consumption, making them less desirable for mobile devices with limited power storage and less efficient for high-performance applications, as they either consume excessive power for maximum performance or compromise performance for reduced power usage.
Innovation Solution
A configurable 3D memory system that dynamically adjusts the use of peripheral logic circuits, allowing memory dies or arrays to either utilize separate or shared decoders and sense amplifiers, enabling adaptive control of power and performance based on system requirements through a memory controller that monitors and adjusts the operating conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate row and column decoders and sense amplifiers are provided for each memory array to achieve maximum performance, then memory access speed and reliability are improved, but power consumption increases significantly
Solution Approach 1:
The patent merges peripheral logic circuits (decoders and sense amplifiers) across multiple memory arrays, allowing shared utilization of these circuits rather than having dedicated separate circuits for each array. This consolidation reduces the total number of peripheral logic circuits required, thereby significantly reducing power consumption while maintaining memory access performance through coordinated sharing of the merged logic resources across arrays.
2Quantity of substance
If stacked memory provides large memory capacity in compact form factor, then memory density is improved, but power consumption becomes significant for mobile applications
Solution Approach 1:
The patent applies merging by consolidating peripheral logic circuits across multiple memory arrays within the stacked memory structure. This allows the large memory capacity to be achieved through multiple arrays while sharing the power-hungry peripheral logic, thereby reducing overall power consumption and making the high-capacity stacked memory suitable for mobile applications with limited power availability.
3Reliability
If stacked memory is designed for maximum performance with dedicated peripheral logic, then reliability is improved, but adaptability to different power requirements is reduced
Solution Approach 1:
The patent implements dynamic configurability in the stacked memory system, allowing the peripheral logic circuits to be dynamically shared or dedicated based on operational requirements. This dynamic architecture enables the memory system to adapt to different power requirements while maintaining reliability, as the system can reconfigure its logic allocation according to the specific application context, whether mobile or high-performance computing.
Data Source
Figure 1
Figure 2A~2B
Figure 3
AI summary
A 3D memory that is configurable for performance and power. An embodiment of a memory device includes a dynamic random-access memory (DRAM) including multiple memory dies, each memory die including multiple memory arrays, each memory array including peripheral logic circuits and a configurable logic. The memory device further includes a system element coupled with the DRAM, the system element including a memory controller. The memory controller is to provide for control of the configurable logic to provide for separate or shared peripheral logic circuits for one or more memory arrays, the configurable logic being configurable to enable or disable one or more of the peripheral logic circuits and to enable or disable one or more I/O connections between the memory arrays.