Configurable Accelerator Logic for Computational Subgraph Execution
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Solution Overview
Problem
Existing data processing systems face inefficiencies in executing complex subgraphs due to the need for specialized hardware, limited support for dependent instructions, and complex configuration processes, which result in increased design and testing costs and hardware overhead.
Innovation Solution
A data processing apparatus with configurable accelerator logic that uses a single look-up table (LUT) configuration for each output function, allowing efficient execution of computational subgraphs by evaluating output functions directly, thereby simplifying configuration and reducing hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If special purpose accelerated hardware is added with specific instructions, then execution speed of complex operations is improved, but device complexity and programming difficulty increase
Solution Approach 1:
The accelerator uses a single LUT configuration that can be dynamically reconfigured to support multiple different computational subgraphs and operations through software control, rather than having dedicated hardware circuits for each operation. This allows one hardware structure to perform many functions that would traditionally require separate specialized circuits.
Solution Approach 2:
The accelerator changes its operational parameters by loading different LUT configurations into the configurable logic. By altering the configuration parameters (LUT contents) rather than the hardware structure itself, the system adapts to different computational requirements, enabling flexible acceleration without physical hardware changes.
2Adaptability or versatility
If multiple versions of programs are written for different hardware platforms, then compatibility with various systems is improved, but development time and maintenance cost increase
Solution Approach 1:
Instead of creating different hardware versions for different platforms, the system uses a single hardware platform with configurable logic that can be software-defined to match different hardware capabilities. The LUT configuration acts as a virtual copy of the desired hardware behavior, allowing one physical device to emulate multiple hardware platforms through software configuration.
Solution Approach 2:
The accelerator transitions from static dedicated hardware to dynamic reconfigurable logic. The configurable accelerator logic can be programmed at runtime to adapt to different computational subgraphs and hardware platforms, providing flexibility without requiring multiple fixed hardware designs or multiple program versions.
3Adaptability or versatility
If subgraphs are identified and control is generated on-the-fly, then adaptability to different programs is improved, but processing overhead increases
Solution Approach 1:
The system performs preliminary identification and classification of computational subgraphs before execution. By analyzing the program structure in advance and pre-determining which subgraphs are candidates for acceleration, the system avoids the need for complex real-time decision-making during execution, reducing runtime overhead while maintaining adaptability.
Solution Approach 2:
The configurable accelerator logic acts as an intermediary between the general-purpose processor and the computational subgraph. It receives control signals, interprets them through the LUT configuration, and executes the appropriate operation, simplifying the control generation process by providing a unified interface for different types of computational operations.
4Productivity
If a 3-input ALU is used to collapse dependent instructions, then execution efficiency is improved, but device complexity and limited functionality increase
Solution Approach 1:
The patent merges multiple independent LUT-based functional units into a single configurable accelerator logic block. Instead of using separate ALUs or functional units for different operations, the system combines them into one reconfigurable structure that can be programmed to perform any of the required computational functions, reducing overall device complexity while maintaining high execution efficiency.
Solution Approach 2:
The patent replaces the mechanical/physical approach of using fixed 3-input ALUs with a software-based configuration system. Instead of relying on hardware circuitry to provide specific functions, the system uses programmable LUT configurations to define the computational logic, substituting physical hardware limitations with flexible software control that can be adapted to any computational requirement.
Data Source
AI summary
A data processing apparatus and method are provided for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs identified within the program. Each computational subgraph has a number of input operands and produces one or more output operands. The apparatus comprises an operand store for storing the input and output operands, and processing logic for executing individual program instructions from the program. Also provided is configurable accelerator logic which, in response to reaching an execution point within the program corresponding to a sequence of individual program instructions corresponding to a computational subgraph, evaluates one or more output functions associated with the computational subgraph. The evaluation of each output function generates an output operand for storing in the operand store, and each output operand corresponds to an output that would have been generated had the sequence of individual program instructions corresponding to the computational subgraph have been executed by the processing logic. Configuration storage stores a single look-up table (LUT) configuration for each output function, and for each output function to be evaluated, the accelerator logic is configured dependent on the associated single LUT configuration from the configuration storage, such that on receipt of the input operands of the computational subgraph, the accelerator logic will generate the output operand. This technique has been found to provide a particularly efficient accelerator logic for evaluating output functions associated with computational subgraphs.