Configurable Bitstream Decoding Engine for Multi-Format Video and Audio
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Solution Overview
Problem
Conventional bit stream engines are inefficient in processing variable length decoding for multiple audio and video formats, particularly at high bit rates, and lack flexibility to handle various encoding schemes, leading to excessive processing power consumption and limited functionality.
Innovation Solution
A configurable bitstream decoding engine that operates in hardware acceleration and hardware assist modes, capable of decoding bitstreams using multiple formats such as MPEG-1, MPEG-2, MPEG-4, WMV9, H.264, JPEG, MP3, AAC, and WMA, with the ability to configure functional components and use downloadable Huffman decode tables for efficient processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single-format variable length decoding engine is used, then the device complexity is reduced, but the adaptability to handle multiple audio and video formats is limited
Solution Approach 1:
The patent implements a universal decoding engine that can handle multiple video formats (MPEG-1, MPEG-2, MPEG-4, H.264, WMV9, JPEG) and audio formats (MP3, AAC, WMA) through a single integrated hardware structure. The engine uses configurable parameters and format-specific lookup tables to adapt to different standards without requiring separate dedicated decoders for each format, thus achieving multi-functionality while controlling complexity.
Solution Approach 2:
The decoding engine employs dynamic configuration capabilities where operational parameters, Huffman tables, and processing modes can be adjusted based on the detected input format. The system dynamically switches between different decoding algorithms and parameter sets depending on whether it processes video or audio data, and which specific standard is being used, allowing adaptability without permanent structural changes.
2Productivity
If a programmable engine is used to accelerate bit stream extraction, then the processing speed is improved, but the efficiency is limited due to software-based computations
Solution Approach 1:
The patent replaces software-based bit stream extraction with dedicated hardware logic circuits that perform extraction operations in parallel. The hardware engine uses bitwise operations, shift registers, and combinatorial logic to extract variable-length fields directly from the bitstream at the hardware level, eliminating the need for software interpretation and significantly reducing CPU involvement and power consumption.
Solution Approach 2:
The system pre-computes and stores Huffman decoding tables, inverse quantization parameters, and other frequently accessed data in hardware-friendly memory structures. These pre-prepared lookup tables allow the hardware engine to perform decoding operations by simple table lookups and bitwise operations rather than complex calculations, improving extraction speed while minimizing real-time processing power requirements.
3Productivity
If conventional software engines with specific instructions are used, then bit processing functions are accelerated, but processing power is wasted on simple calculations and lookups
Solution Approach 1:
The patent implements dedicated hardware circuits for Huffman decoding, inverse quantization, and bit field extraction operations. These hardware blocks perform what would otherwise be software-based calculations and table lookups through parallel bitwise operations and combinatorial logic, eliminating the overhead of software execution and reducing CPU cycle consumption for these routine operations.
Solution Approach 2:
The decoding engine is divided into specialized functional blocks: a bit stream extraction unit, a Huffman decoding unit with format-specific tables, an inverse quantization unit, and an entropy decoding unit. Each segment handles specific operations in hardware, allowing simple calculations and lookups to be performed by dedicated logic rather than general-purpose processors, thus avoiding power waste while maintaining high processing speed.
4Productivity
If hardware acceleration mode is used, then the decoding speed is improved, but the device complexity increases
Solution Approach 1:
The patent integrates multiple decoding functions (Huffman decoding, inverse quantization, entropy decoding, bit stream extraction) into a single unified hardware engine. By merging these functions into one coordinated system with shared control logic and common data paths, the design achieves high decoding speed without proportionally increasing overall device complexity compared to having separate hardware blocks for each function.
Data Source
AI summary
Configurable bitstream engines are described that can operate to decode variable length decoding of video and audio bitstreams encoded using any of a plurality of encoding schemes. Systems and methods are described that allow functional components of a bitstream engine to be disabled, enabled and configured as necessitated by the encoding scheme used to encode a bitstream. Functional components of a bitstream engine can perform single actions and operations, repetitive actions and operations and sequences of actions and operations as desired. A bit field extraction process is described for extracting bit fields of specified length from memory, updating bit offsets, loading new data from memory when needed.