Configurable Cache Access Policies for DRAM Latency
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Solution Overview
Problem
The increasing memory access latency in computer systems due to the growing processing speed and storage capacity of DRAM is not effectively addressed by traditional cache devices, which often result in inefficient data eviction and storage policies, leading to performance degradation.
Innovation Solution
A cache device with a configurable access policy that includes a tag array, a data array, and a cache controller, which receives cache access requests and determines the appropriate policy to store, evict, or bypass data based on indications from the processor, allowing for tailored data management according to specific sequences of operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional cache devices are used with fixed access policies, then the cache structure is simple, but the cache operation efficiency deteriorates due to inability to adapt to different data access patterns
Solution Approach 1:
The patent implements dynamic cache access policies where the cache controller can selectively differentiating between read and write operations based on incoming requests. The policy selection logic dynamically determines whether to apply read policies (e.g., read-allocate, read-no-allocate) or write policies (e.g., write-back, write-through, write-allocate, write-no-allocate) depending on the operation type and system state, making the cache behavior adaptive rather than static
Solution Approach 2:
The patent changes the operational parameters of the cache by introducing configurable policy selections for read and write operations. The cache controller modifies its behavior by selecting different access policies based on parameters such as operation type (read/write), cache state, and system conditions, allowing the same cache structure to operate under multiple policy regimes without physical reconfiguration
2Quantity of substance
If DRAM storage capacity and processing speed increase according to Moore's Law, then storage capacity and processing speed improve, but memory access latency worsens and becomes a bottleneck
Solution Approach 1:
The patent segments the memory hierarchy into multiple cache levels (L1, L2, L3 caches) with different capacities, speeds, and access policies. Each cache level handles different types of data access patterns and can be independently configured with appropriate read and write policies, allowing the system to optimize for both capacity and latency by distributing data across multiple segmented cache structures
Solution Approach 2:
The patent introduces multiple cache levels as intermediaries between the processor and DRAM. These cache levels act as mediators that can store frequently accessed data closer to the processor, reducing the frequency of slow DRAM accesses. The cache controller mediates access requests by determining whether data can be served from cache or must be fetched from DRAM, thereby reducing overall access latency
3Speed
If data is stored in cache to speed up future access, then access speed improves, but cache storage space is consumed requiring data eviction
Solution Approach 1:
The patent implements dynamic eviction policies that adapt to different write operation types. For write-back policy, modified data is kept in cache until eviction, maximizing cache utilization. For write-through policy, data is immediately propagated to lower memory levels, allowing faster cache turnover. The controller dynamically selects eviction strategies based on the write policy and access patterns, optimizing the balance between keeping useful data in cache and making room for new data
Data Source
AI summary
A cache is presented. The cache comprises a tag array configured to store one or more tag addresses, a data array configured to store data acquired from a dynamic random access memory device, and a cache controller. The cache controller is configured to: receive a cache access request; determine, based on an indication associated with the cache access request, a cache access policy; and perform an operation to the tag array and to the data array based on the determined cache access policy.