Configurable Cache System for Instruction Type Linefills
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Microprocessor cache systems face performance issues due to cache misses, especially in L1 caches, which are small and prone to 'pollution' by data with low spatial and temporal locality, leading to inefficient use of space and increased access times.
Innovation Solution
The system differentiates between two types of load/store instructions based on their operational codes, with one type (e.g., integer loads) performing L1 cache linefills on misses and the other type (e.g., SIMD loads) avoiding L1 cache linefills, allowing the L2 cache to function as an L1 cache for data with low locality, thereby optimizing cache usage and reducing processor stalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If L1 cache linefills are performed on all load instructions, then cache hit rate is improved, but processor performance deteriorates due to pollution by low locality data
Solution Approach 1:
The patent applies local quality by treating different instruction types differently with respect to L1 cache linefills. Load instructions are categorized into those that benefit from L1 linefills (e.g., integer loads with high locality) and those that do not (e.g., SIMD loads with low locality). The cache control logic selectively performs linefills only for beneficial instruction types, making the cache behavior locally optimized rather than uniformly applied.
Solution Approach 2:
The patent changes the parameter of cache linefill behavior based on instruction type. By decoding the instruction type and selectively enabling or disabling L1 linefills, the system dynamically adjusts cache operation parameters to match the characteristics of the accessed data, thereby avoiding pollution from low locality data while maintaining high hit rates for suitable data.
2Reliability
If L1 cache size is increased to reduce misses, then cache hit rate is improved, but device complexity and cost increase
Solution Approach 1:
Instead of changing the physical size parameter of the L1 cache, the patent changes the operational parameter of linefill behavior. By selectively enabling linefills based on instruction type, the system optimizes cache effectiveness without increasing cache capacity or physical complexity.
3Productivity
If L1 cache linefills are avoided for low locality data, then processor performance is improved, but cache hit rate deteriorates
Solution Approach 1:
The patent applies local quality by differentiating between instruction types and applying appropriate cache linefill strategies to each. Load instructions with high locality characteristics receive L1 linefills to maximize hit rates, while those with low locality characteristics skip linefills to avoid pollution, thereby optimizing overall processor performance without uniformly sacrificing hit rates.
Data Source
Figure 1~3
Figure 2
AI summary
A processor (51) comprises decode logic (54) that determines an instruction type for each instruction fetched, a first level cache (Ll), a second level cache (L2) coupled to the first level cache, and control logic operatively coupled to the first and second level caches. The control logic preferably causes cache linefills to be performed to the first level cache upon cache misses for a first type of instruction, but precludes linefills from being performed to the first level cache for a second type of instruction.