Configurable Cache Allocation for Multi-Core Memory Coherency
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Solution Overview
Problem
Multi-core systems face coherency issues due to shared memory access, leading to operational inefficiencies and challenges in maintaining data consistency across processing cores, particularly when software cache maintenance operations are slow or resource-intensive.
Innovation Solution
A multi-core shared memory controller (MSMC) is implemented with a snoop filter bank, cache tag bank, and memory bank, which includes a coherent slave interface, external memory master interface, and an arbiter circuit to manage memory access requests, determine snoop requests, and allocate virtual channels, ensuring coherent data access and reducing operational inefficiencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software cache maintenance operations are used to maintain coherency, then data consistency can be achieved, but operational efficiency deteriorates due to slow performance and excessive operational time consumption
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based coherency monitoring system. The snoop filter bank and cache tag bank operate in hardware to automatically detect and resolve coherency issues, eliminating the need for software interventions and significantly improving operational efficiency while maintaining data consistency
Solution Approach 2:
The patent introduces a hardware intermediary system consisting of the snoop filter bank and cache tag bank that mediates between multiple cores accessing shared memory. This intermediary automatically monitors cache states and coordinates access patterns, resolving coherency issues without requiring software cache maintenance operations
2Productivity
If hardware-based coherency monitoring is implemented with snoop filter bank and cache tag bank, then operational efficiency improves, but device complexity increases
Solution Approach 1:
The patent merges the snoop filter bank and cache tag bank into a unified hardware structure within the memory controller. By combining these functions into an integrated system that operates simultaneously, the patent reduces overall complexity compared to having separate, distributed coherency monitoring mechanisms across multiple cores
Solution Approach 2:
The hardware-based coherency monitoring system performs multiple functions simultaneously: it monitors cache states, detects coherency violations, and coordinates access patterns across multiple cores. This multi-functional approach consolidates what would otherwise require separate mechanisms, reducing overall device complexity
Data Source
AI summary
A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.