Configurable Cache Segmentation for Cross Thrashing Reduction
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Solution Overview
Problem
Conventional multimedia SoCs face challenges with cross thrashing due to multiple processing components accessing a shared cache, leading to increased latency and decreased throughput, as each component continually overwrites the cache, forcing them to fetch data from main memory, which limits bandwidth and fails to meet latency requirements.
Innovation Solution
A system utilizing a qualifier-based splitter, configurable caches, and an arbiter to route transactions and manage cache access, enabling dynamic configuration of prefetching, write modes, and replacement policies, reducing cross thrashing and optimizing cache performance for each processing component.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a shared cache is used by multiple processing components, then memory bandwidth utilization is improved, but cross thrashing occurs leading to increased latency and decreased throughput
Solution Approach 1:
The cache is divided into multiple independent ways (e.g., 4 ways), with each way dedicated to a specific processing component. This segmentation eliminates cross thrashing by ensuring that each processor has its own cache way, preventing one processor from evicting another's data while still utilizing the full cache bandwidth through parallel access to different ways.
2Loss of time
If cache size is increased to reduce cross thrashing, then latency is decreased, but cache access speed decreases due to larger cache size
Solution Approach 1:
Rather than increasing overall cache size, the invention segments the existing cache into multiple ways. Each processor accesses its dedicated way, maintaining fast access speeds while reducing cross thrashing. This approach achieves latency reduction without the performance penalty of enlarging the cache.
3Loss of time
If partitioned caches are used to eliminate cross thrashing, then latency is decreased, but device complexity increases and large cache size is required
Solution Approach 1:
The cache is segmented into multiple ways with each way dedicated to a specific processor through qualifier-based routing. The splitter component automatically routes cache requests to the appropriate way based on qualifiers, eliminating the need for complex software-based cache partitioning schemes while reducing cross thrashing and latency.
Solution Approach 2:
A qualifier-based splitter acts as an intermediary between processors and the cache, automatically routing requests to the appropriate cache way based on qualifiers. This intermediary simplifies cache management by handling the partitioning logic centrally, reducing the complexity that would otherwise be required in software-based approaches.
4Productivity
If dynamic configuration of cache parameters is implemented, then cache performance is optimized for different processing components, but device complexity increases
Solution Approach 1:
The cache system implements dynamic configuration where parameters such as prefetching, write modes, and replacement policies can be independently adjusted for each cache way. This allows optimization for different processing components while maintaining manageable complexity through the qualifier-based routing architecture that automatically directs requests to the appropriately configured way.
Data Source
AI summary
A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter component. The first data processing component generates a first request for a first portion of data at a first location within a memory. The second data processing component generates a second request for a second portion of data at a second location within the memory. The qualifier based splitter component routes the first request and the second request based on a qualifier. The first configurable cache element enables or disables prefetching data within a first region of the memory. The second configurable cache element enables or disables prefetching data within a second region of the memory. The arbiter component routes the first request and the second request to the memory.