Configurable Cache Way Redundancy for Dynamic Error Detection
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Solution Overview
Problem
Traditional cache memories are limited in detecting multiple faults per byte, requiring increased Hamming distance for higher fault tolerance, which complicates the system and reduces performance, necessitating a configurable solution that balances robustness and performance.
Innovation Solution
A data processing system with a multi-way cache that allows configuration between independent associative modes and redundant modes, enabling dynamic error detection and correction based on user needs, using a processor with a first and second way that can operate independently or redundantly, and error detection logic to compare data from both ways for error signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the Hamming distance is increased to four for higher fault tolerance, then the robustness of the cache memory is improved, but the system complexity increases and performance decreases
Solution Approach 1:
The patent implements a configurable second way that can dynamically switch between two operational modes: independent associative mode for normal operation and redundant mode for error detection. This dynamic reconfiguration allows the system to adapt its structure based on whether fault tolerance is needed, avoiding permanent complexity while providing on-demand reliability.
Solution Approach 2:
The patent changes the operational parameter of the second way from fixed to variable, allowing it to transition between independent and redundant configurations. By controlling the operational mode through configuration bits, the system can adjust its error detection capability without permanently increasing complexity, resolving the contradiction between reliability and device complexity.
2Reliability
If the Hamming distance is increased to four for higher fault tolerance, then the robustness of the cache memory is improved, but the performance of the cache memory decreases
Solution Approach 1:
The configurable second way enables the system to dynamically activate redundant mode only when fault tolerance is required, rather than always operating with full error detection overhead. This on-demand approach maintains high performance during normal operation while providing robustness when needed, resolving the performance-reliability tradeoff.
Solution Approach 2:
By changing the operational parameter of the second way between independent and redundant modes, the system can adjust its performance profile. In independent mode, performance is maximized with no overhead; in redundant mode, fault tolerance is enabled with minimal performance penalty, thus resolving the contradiction between productivity and reliability.
3Productivity
If the second way operates as an independent associative way, then the performance of the cache memory is improved, but the fault detection capability is reduced
Solution Approach 1:
The patent makes the second way dynamically configurable between independent and redundant modes, allowing the system to switch its operational characteristics based on requirements. This resolves the contradiction by enabling the second way to serve different functions at different times, optimizing both performance and error detection capability as needed.
Solution Approach 2:
The second way is designed to perform multiple functions: it can operate as an independent associative way for high-performance operation or as a redundant way for error detection. This multi-functionality allows a single structure to satisfy both performance-oriented and reliability-oriented requirements, resolving the contradiction between productivity and reliability.
Data Source
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AI summary
A data processing system (10) includes a processor (12) having a multi-way cache (60) which has a first (64, 72) and a second (66, 74) way. The second way is configurable to either be redundant to the first way or to operate as an associative way independent of the first way. The system may further include a memory (18), where the processor (12), in response to a read address missing in the cache (60), provides the read address to the memory (18). The second way may be dynamically configured to be redundant to the first way during operation of the processor (12) in response to an error detection signal. In one aspect, when the second way is configured to be redundant, in response to the read address hitting in the cache (60), data addressed by an index portion of the read address is provided from both the first and second way and compared to each other to determine if a comparison error exists.