Configurable Clock Macro Circuit for Structured ASIC Routing
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Solution Overview
Problem
Structured ASIC devices face inefficiencies in clock structure design, leading to suboptimal clock frequencies and resource usage due to dedicated clock circuits and lack of integrated DFT functionality, which complicates engineering change orders and increases design closure time.
Innovation Solution
A configurable clock macro circuit is implemented using programmable masks in structured ASIC devices, allowing for various clock functions such as buffers, inverters, gates, multiplexers, and shapers, thereby optimizing clock network design and resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dedicated clock circuits are used in structured ASIC devices, then clock signal distribution is simplified, but resource usage efficiency decreases and device area increases
Solution Approach 1:
The patent implements a universal logic unit that can be configured to perform multiple clock circuit functions (buffer, inverter, gate, multiplexer, shaper) through programmable interconnects and configurable logic elements. This single reconfigurable unit replaces multiple dedicated clock circuits, improving resource usage efficiency while maintaining the ability to distribute clock signals throughout the device.
Solution Approach 2:
The clock circuit functionality is made dynamic and reconfigurable through programmable interconnects and configurable logic elements that can be programmed after fabrication. This allows the same physical hardware to adapt its behavior based on design requirements, enabling efficient resource usage while providing flexible clock signal distribution capabilities.
2Ease of manufacture
If dedicated clock circuits are used in structured ASIC devices, then clock signal routing is simplified, but device area increases
Solution Approach 1:
The configurable logic elements and programmable interconnects form a universal platform that can implement various clock circuit functions (buffers, inverters, gates, multiplexers, shapers) in software-defined manner. This eliminates the need for multiple dedicated clock circuit blocks, significantly reducing device area while maintaining simplified clock signal routing through the programmable interconnect fabric.
Solution Approach 2:
The patent merges the functionality of multiple dedicated clock circuits (buffers, inverters, gates, multiplexers, shapers) into a single reconfigurable logic unit. By combining these previously separate dedicated circuits into one unified configurable structure, the device area is reduced while the programmable interconnects maintain the simplified routing capability.
3Adaptability or versatility
If separate clock circuits are used for positive and negative edge triggering, then clock functionality is enhanced, but device complexity increases
Solution Approach 1:
The configurable logic element is designed to universally handle both positive edge-triggered and negative edge-triggered clock functionality through a single unit. By using programmable interconnects and configurable logic, the same physical circuit can be programmed to provide either positive or negative edge triggering as needed, eliminating the need for separate dedicated circuits for each edge type and reducing device complexity.
4Adaptability or versatility
If mask programming is used for configuring vias, then adaptability is improved, but design closure time increases
Solution Approach 1:
The patent performs clock circuit configuration through mask programming during the fabrication process itself, rather than requiring post-fabrication reconfiguration. By preliminary configuring the vias and interconnects during manufacturing, the design is locked in before delivery to the customer, significantly reducing design closure time while maintaining the adaptability to configure different clock circuit functions through the mask programming process.
Data Source
AI summary
An integrated circuit includes a clock macro circuit. The clock macro circuit includes first, second, and third latch circuits and a multiplexer circuit. The first latch circuit is coupled to the second latch circuit. The multiplexer circuit is coupled to the second and third latch circuits. The clock macro circuit includes programmable vias that are programmed during fabrication of the integrated circuit to couple inputs of the clock macro circuit to the first latch circuit, the second latch circuit, the third latch circuit, and the multiplexer circuit. Programming the programmable vias causes the clock macro circuit to function as a selected type of clock circuit.