Configurable Correlator Bank for Fast DSSS Detection

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Solution Overview

Problem

Existing IoT wireless communication devices face challenges in efficiently handling multiple wireless protocols due to large size and cost from multiple integrated circuits, and current demodulators experience latency and dropped communications during protocol switching, with non-coherent DSSS demodulators having slow signal arrival detection in low SNR environments.

Innovation Solution

A demodulator with a configurable correlator bank configured for signal arrival, coarse timing, and despreading, utilizing function transformations and correlator configurations for fast DSSS signal detection and accurate timing and frequency offset estimation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a non-coherent DSSS demodulator is used to eliminate complex synchronization circuit architectures, then device complexity is reduced, but signal arrival detection speed deteriorates in low SNR environments

Engineering Contradiction:
Improvesynchronization circuit architectureVSAvoidsignal arrival detection speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The correlator bank is divided into multiple independent correlators (e.g., 8 correlators) that can be independently configured and operated. Each correlator processes different aspects of signal detection, allowing parallel operation to achieve fast signal arrival detection without requiring complex centralized synchronization circuits.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The correlator bank is designed to be reconfigurable, serving multiple functions including signal arrival detection, coarse timing synchronization, fine timing synchronization, and frequency offset estimation. This multi-functionality eliminates the need for separate dedicated circuits for each function, reducing overall device complexity while maintaining high detection speed.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If firmware stops current demodulator operations to switch between wireless protocols, then protocol switching capability is achieved, but communication latency increases and dropped communications occur

Engineering Contradiction:
Improveprotocol switching capabilityVSAvoidcontext switch latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The correlator bank configuration is made dynamic and reconfigurable, allowing the system to switch between different protocol modes (e.g., BLE mode, 802.15.4 mode) without complete demodulator shutdown. The correlators can be dynamically reconfigured to match different protocol requirements, enabling seamless protocol switching with minimal latency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system maintains the demodulator in a ready state with correlators pre-configured or quickly reconfigurable, allowing protocol switching to occur without complete operational shutdown. This preliminary preparation reduces context switch latency and prevents communication drops during protocol transitions.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If a single demodulator is used to reduce device size and cost, then device complexity is reduced, but the ability to simultaneously receive multiple wireless protocols deteriorates

Engineering Contradiction:
Improvenumber of integrated circuitsVSAvoidmulti-protocol reception capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The single demodulator incorporates a reconfigurable correlator bank that can be dynamically configured to support multiple wireless protocols (BLE, 802.15.4, etc.). The correlators can be reconfigured to match different protocol-specific parameters such as preamble lengths, chip rates, and synchronization sequences, enabling one demodulator to perform the work of multiple dedicated demodulators.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The correlator bank uses dynamic reconfiguration to adapt to different protocol requirements in real-time. Control logic dynamically adjusts correlator parameters and configurations based on the target protocol, allowing the single demodulator to efficiently handle multiple protocols without requiring separate hardware for each protocol.

Inventive Principle:
Principle #15Dynamics

4Measurement precision

If a DSSS demodulator performs signal arrival detection to detect protocol transmissions, then protocol detection capability is improved, but other wireless protocol traffic is blocked during detection

Engineering Contradiction:
Improvesignal arrival detection accuracyVSAvoidthroughput of other protocols
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The correlator bank is segmented into multiple correlators that can operate in parallel. During signal arrival detection for one protocol, other correlators can simultaneously process traffic for other protocols, preventing blocking and maintaining throughput across multiple protocols while achieving accurate detection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The correlator bank is designed to handle multiple protocols simultaneously through its reconfigurable nature. While one set of correlators performs signal arrival detection for a specific protocol, other correlators can concurrently process other protocol traffic, eliminating the blocking effect and maintaining high productivity across all protocols.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12413464B2Configurable correlator bank for a non-coherent DSSS demodulator
Publication Date: 2025.09.09 SILICON LABORATORIES INC
  • US12413464B2 patent drawing
  • US12413464B2 patent drawing
  • US12413464B2 patent drawing

AI summary

A demodulator has a correlator bank with multiple correlators. The correlator bank has multiple configurations, including a signal arrival configuration, a coarse timing configuration, and a despreading configuration. The various configurations are used to correlate function transformations of received symbols to template signals. Each correlator has elements with a number of delay blocks corresponding to a number of chips in a symbol. The output of each delay block is multiplied by a bit of a template signal by negating or not negating the output and the multiplications results are summed. A function transformations block receives phase information to generate the function transformations, which are supplied to the correlators. The function transformations include a transformation with a one chip differential, transformations with multi-chip differentials, an average transformation that includes an average of a one-chip phase difference between two adjacent samples, and a second order phase differentiation used for frequency deviation correlation.