Configurable Cyclic Code Encoder Using Shared Generator Polynomials
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Solution Overview
Problem
Existing error correction coding systems lack configurability to efficiently support multiple different codes, leading to hardware duplication, increased size, cost, and power consumption in applications requiring varied channel conditions and data types.
Innovation Solution
A configurable ECC encoder system with two processing stages and ancillary circuitry that operates in multiple modes, filtering input data with coefficients of a first and second generator polynomial, generating redundancy outputs for each mode, and selectively activating stages based on requested codes, exploiting the commonality between generator polynomials of different cyclic codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate encoders are used for different cyclic codes, then each code can be encoded independently and reliably, but hardware size and power consumption increase due to duplication
Solution Approach 1:
The encoder is designed with a universal structure that can encode multiple different cyclic codes (BCH codes with different error correction capabilities) using the same hardware resources. The encoder includes configurable elements such as programmable coefficient sets and selectable processing modes that allow it to adapt to different code requirements without requiring separate dedicated encoders for each code type.
Solution Approach 2:
The encoder incorporates dynamic reconfiguration capabilities through programmable coefficient sets and selectable processing modes. The coefficient sets can be loaded and switched based on the required code type, and the processing mode can be dynamically adjusted to match the specific encoding requirements, enabling the same hardware to reliably handle multiple different cyclic codes.
2Adaptability or versatility
If multiple separate encoders are implemented to support varied channel conditions, then all channel conditions can be covered, but cost and power consumption increase
Solution Approach 1:
The encoder provides universal support for multiple channel conditions by implementing a single hardware structure that can be configured for different cyclic codes suitable for various channel conditions. The programmable coefficient sets and selectable processing modes enable the encoder to adapt to different error rates and channel characteristics without requiring multiple separate encoder units.
Solution Approach 2:
The encoder changes its operational parameters (coefficient sets, processing modes) based on the required code type and channel conditions. By programmatically loading different coefficient sets and switching between processing modes, the encoder can optimize its performance for specific channel conditions while consuming the same base power as a single encoder configuration.
3Area of stationary object
If a configurable encoder is designed to support multiple codes, then hardware duplication is reduced, but device complexity increases
Solution Approach 1:
The encoder is segmented into functional modules including coefficient storage units, processing units, and control logic. Each module has a specific function, and they work together through standardized interfaces. This modular segmentation reduces overall complexity by making each component simpler and more specialized, while the system as a whole maintains the capability to encode multiple different cyclic codes.
4Reliability
If separate processing stages are used for different codes, then each code can be processed optimally, but productivity decreases due to sequential processing
Solution Approach 1:
The processing stages are designed to be dynamically selectable rather than fixed and sequential. The encoder can switch between different processing modes and activate only the necessary stages for the current code type, enabling parallel or pipelined processing when appropriate. This dynamic approach maintains processing accuracy for different codes while improving overall encoding speed and throughput.
Data Source
AI summary
Apparatus for encoding includes a first processing stage, which is configured to filter input data with a first set of coefficients belonging to a first generator polynomial representing a first ECC, to produce a first output. A second processing stage is configured to filter the first output using a second set of coefficients belonging to a quotient polynomial, which is defined as a quotient of a second generator polynomial, representing a second ECC, divided by the first generator polynomial, to produce a second output. Ancillary circuitry has first and second operational modes and is coupled to the first and second processing stages so as to generate a first redundancy output corresponding to the first ECC based on the first output when operating in the first mode, and to generate a second redundancy output corresponding to the second ECC based on the second output when operating in the second mode.