Configurable Data Path Architecture for Flexible Clocking
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Solution Overview
Problem
Conventional data paths in integrated circuits lack flexibility in accommodating various data clocking configurations, burst lengths, and sequences, making them unsuitable for multiple functions and requiring complex redesigns for each variation.
Innovation Solution
A configurable data path with a de-multiplexer, parallel latches, and registers, along with burst address generators and write buffers, allowing for flexible data input and output in multiple modes, including sequential and parallel operations, to accommodate different clocking types and burst sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional data paths are used with fixed manufacturing options, then device complexity is reduced, but adaptability to different clocking configurations and burst sequences is lost
Solution Approach 1:
The data path employs dynamic control signals (en1, en2, en3) that can be configured through manufacturing options to enable different operational modes (single/double clocking, various burst lengths). The same physical structure adapts its behavior through these configurable enable signals, allowing a single data path to serve multiple functions without requiring separate hardwired circuits for each mode.
Solution Approach 2:
The data path is designed as a universal structure that can perform multiple functions through configurable control. The same registers, latches, and multiplexers can operate in different modes (single clocking, double clocking, various burst lengths) by changing the control signal configurations, eliminating the need for separate dedicated paths for each function.
2Adaptability or versatility
If multiple manufacturing options are provided for different burst lengths and sequences, then adaptability is improved, but device complexity increases
Solution Approach 1:
The data path is segmented into distinct controllable sections with dedicated enable signals (en1 for first latch, en2 for second latch, en3 for register). Each segment can be independently controlled to accommodate different burst lengths. For example, to achieve a burst length of 2, only the first latch is enabled; for burst length of 4, both latches and registers are enabled. This segmentation allows flexible configuration without requiring complex redesign.
3Ease of operation
If conventional fixed data paths are used, then manufacturing simplicity is maintained, but timing flexibility for different clocking types is reduced
Solution Approach 1:
The data path utilizes parameter changes in the control signals (en1, en2, en3) to achieve different timing behaviors. By changing which enable signals are active during manufacturing, the same physical circuit can be configured for different clocking types (single or double clocking) and burst lengths. This allows timing flexibility to be achieved through parameter configuration rather than physical redesign.
Data Source
AI summary
Data paths (100 and 900) can be configured to accommodate two or four burst data sequences, with a data value being input/output each half clock cycle. A data sequence can be a fixed order or user-defined order depending upon a selected option. A data input path (100) can reduce power consumption with an enable signal (dinen) timed to activate after data input lines have settled values. A data output path (900) can access output data in a parallel fashion for subsequent output according to a burst sequence. Cycle latencies for such output data can include one clock cycle latency or one and a half-clock cycles. A data output path (900) can also accommodate various clocking modes, including: single clocking with a delay locked loop (DLL) type circuit enabled, single clocking with a delay locked loop (DLL) type circuit disabled, and double clocking, with a phase difference between an input clock and output clock of up to 180°.