Configurable Delay Circuit for SRAM Clock Buffering
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Solution Overview
Problem
In VLSI circuit design, particularly in SRAM, controlling the arrival times of critical signals is challenging due to increasing nonlinearities and tighter timing constraints, as well as variations across process, voltage, and temperature (PVT) corners, which are exacerbated by multi-power-domain designs. Existing solutions either introduce performance penalties or consume more area.
Innovation Solution
A configurable delay circuit in SRAM that uses a plurality of transistor stacks to form a delay path, selectively coupled by a delay path select circuit, allowing for dynamic adjustment of the delay based on desired timing constraints, thereby buffering the clock signal without excessive area or performance penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed margins or delays are introduced to accommodate worst case latency, then signal arrival time constraints are met, but system performance is penalized due to overly conservative timing
Solution Approach 1:
The patent implements dynamic delay adjustment by replacing fixed delay margins with configurable delay circuits that can be tuned based on actual operating conditions. The delay amount is adjusted dynamically according to process, voltage, and temperature variations, allowing the system to meet timing constraints without excessive conservative margins that would penalize performance.
2Productivity
If multiple delay paths are multiplexed to reduce performance penalties, then system performance is improved, but circuit area increases
Solution Approach 1:
The patent segments the delay function into multiple configurable delay elements that can be selectively activated. Instead of providing multiple complete delay paths, the delay path is divided into segments that can be individually enabled or disabled based on timing requirements, reducing the total area compared to fully multiplexed delay paths.
Solution Approach 2:
The patent uses dynamic selection of delay elements through control logic that adjusts which delay segments are activated based on operating conditions. This dynamic configuration allows the circuit to achieve variable delay without requiring multiple complete static delay paths, thereby reducing area while maintaining performance flexibility.
3Loss of time
If transistor stacks are added to increase delay, then signal arrival time is adjusted, but circuit area increases
Solution Approach 1:
The patent segments the delay function into multiple transistor stack elements that can be selectively connected in series. By dividing the delay function into segments, the circuit can achieve the required total delay by activating only the necessary number of segments, rather than always requiring the full area of maximum delay elements.
Solution Approach 2:
The patent implements partial delay by allowing selective activation of transistor stacks based on actual timing requirements. Instead of always providing maximum delay capability, the circuit activates only the partial delay needed for current operating conditions, thereby reducing area consumption while maintaining the ability to provide full delay when required.
Data Source
AI summary
An SRAM clock circuit and an SRAM. In one embodiment, the SRAM clock circuit includes: (1) a plurality of transistor stacks optionally serially electrically couplable to form a configurable delay path through which a clock signal is buffered, and (2) a delay path select circuit respectively electrically coupled between pairs of the plurality of transistor stacks and operable to selectively electrically couple the plurality of transistor stacks to a base delay path, thereby activating the configurable delay path based on a desired delay.