Configurable Delay Elements for Data-Bus Signal Timing Skew
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Solution Overview
Problem
Data bus interfaces in electronic devices face timing skew issues due to variations in signal routing, manufacturing processes, and voltage changes, leading to degraded signal integrity and restricted PCB layout when trying to sample multiple signals with a single sampling timing.
Innovation Solution
A method and apparatus that use configurable delay elements to individually align logic signals to a common sampling timing, compensating for timing skews by selecting appropriate time delays that center or overlap timing windows, and considering voltage variations to position the sampling point at the centroid of a voltage-timing plane.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual time delays are applied to align each logic signal to common sampling timing, then signal integrity is improved, but device complexity increases due to configurable delay elements
Solution Approach 1:
The patent divides the timing alignment function into individual configurable delay elements for each logic signal. Each delay element can be independently adjusted to compensate for timing skew in its respective signal, allowing precise alignment to the common sampling timing while maintaining modularity and manageability of the overall system.
Solution Approach 2:
The patent applies different time delay values to different logic signals based on their individual timing characteristics. Each signal receives a customized delay adjustment tailored to its specific routing and skew characteristics, rather than applying a uniform delay to all signals, thereby optimizing signal integrity for each individual path.
2Measurement precision
If timing windows are centered on common sampling timing, then sampling accuracy is improved, but timing constraints on PCB layout become more restrictive
Solution Approach 1:
The patent performs timing window identification and delay selection in advance during the calibration phase. By determining the optimal delay values beforehand based on identified timing windows, the system establishes a common sampling timing that accommodates all signals without requiring tight PCB layout constraints during normal operation.
Solution Approach 2:
The patent introduces configurable delay elements that can be dynamically adjusted to compensate for timing variations. This dynamic adjustment capability allows the system to adapt to different PCB layouts and signal routing configurations while maintaining accurate sampling, thereby relaxing the strictness of timing constraints on PCB design.
3Ease of manufacture
If individual delay elements are configured within finite delay range, then implementation feasibility is improved, but timing window coverage may be limited
Solution Approach 1:
The patent identifies timing windows for each logic signal and selects delay values that ensure the delayed signals overlap at the common sampling timing. By focusing on achieving sufficient overlap rather than maximizing individual signal margins, the system achieves reliable sampling within the finite delay range of practical delay elements.
Solution Approach 2:
The patent creates a calibrated timing model by identifying timing windows and determining optimal delay values during a calibration phase. This pre-determined delay configuration serves as a reference that can be replicated across different operating conditions, ensuring consistent timing window coverage without requiring real-time adjustment beyond the finite delay range.
Data Source
AI summary
A method includes receiving a group of logic signals to be sampled at a common sampling timing. Individual time delays, which individually align each of the logic signals to the common sampling timing, are selected for the respective logic signals in the group. Each of the logic signals is delayed by the respective selected individual time delay, and the entire group of the delayed logic signals is sampled at the common sampling timing.