Configurable Deserializer Circuit for Multi-Rate PLD Receivers
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Solution Overview
Problem
High-speed serial data receiver circuitry in programmable logic devices (PLDs) lacks flexibility to support various communication protocols and data rates, limiting its ability to deserialize serial data efficiently across a wide range of data rates from 622 Mbps to 6.5 Gbps.
Innovation Solution
The deserializer circuitry is designed to be configurable and reconfigurable, capable of converting serial data to parallel data of different widths (8, 10, 16, or 20 bits) and operating at various frequencies, using multi-phase recovered clock signals and dynamic re-configuration RAM control to support multiple communication standards and protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional deserializer circuitry is used, then the circuit can support a limited range of data rates, but it lacks flexibility to support various communication protocols and data widths
Solution Approach 1:
The deserializer circuit is designed with universal functionality to support multiple communication protocols (SONET, Fibre Channel, InfiniBand, PCI Express) and various data widths (8, 10, 16, or 20 bits) through a single unified architecture. The circuit uses configurable parameters including parallel data width selection, data rate selection, and half-rate mode enablement to adapt to different protocol requirements without requiring separate dedicated circuits for each protocol
Solution Approach 2:
The deserializer employs dynamic reconfiguration capabilities through control signals that can change operational parameters during operation. The circuit includes configurable elements such as selectable parallel data widths, adjustable data rates ranging from 622 Mbps to 6.5 Gbps, and dynamic enabling of half-rate mode, allowing the circuit to adapt its behavior based on the specific communication protocol and data width requirements
2Adaptability or versatility
If the deserializer is configured to support a wide range of data rates from 622 Mbps to 6.5 Gbps, then versatility is improved, but circuit complexity increases
Solution Approach 1:
The deserializer achieves wide data rate support (622 Mbps to 6.5 Gbps) by implementing configurable parameters including data rate selection mechanisms and half-rate mode enablement. The circuit uses parameter-based configuration to adapt its operational characteristics to different data rates without requiring fundamentally different circuit architectures for each rate
3Adaptability or versatility
If multiple demultiplexing stages are used to achieve flexible data width conversion, then adaptability is improved, but power consumption and circuit elements increase
Solution Approach 1:
The deserializer implements segmented demultiplexing architecture with multiple stages (first demultiplexing stage and second demultiplexing stage) that can be selectively activated. The circuit supports configurable parallel data widths of 8, 10, 16, or 20 bits by enabling or disabling specific demultiplexing stages, allowing flexible data width conversion while managing power consumption through selective activation of circuit segments
Data Source
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AI summary
Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device ("PLD") or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).