Configurable Error Detection Unit for Multi-Core Systems
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Solution Overview
Problem
Existing methods for detecting execution errors in multi-CPU systems, such as the lock-step verification technique, incur significant hardware overhead, making them impractical for large numbers of CPUs and economically unfeasible.
Innovation Solution
A data processing device with an error detection unit comprising a processor and configurable circuitry that compares results from multiple sequences of instructions executed on different cores, using watchdog timers to monitor execution times and prevent further execution if errors are detected, thereby reducing hardware overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lock-step verification technique with hardware comparators is used to detect execution errors, then error detection capability is improved, but hardware overhead increases significantly
Solution Approach 1:
The patent replaces the mechanical hardware comparator system with a software-based error detection mechanism. Instead of using dedicated hardware comparators to continuously monitor CPU outputs, the system uses software modules that periodically check execution results and compare them against expected values or previous states, thereby eliminating the need for complex hardware overhead while maintaining error detection capability.
Solution Approach 2:
The patent creates a virtual copy of the CPU execution state through software logging and checkpointing mechanisms. Rather than physically duplicating hardware components to monitor each CPU, the system creates software-based replicas of execution states that can be compared and validated, reducing hardware requirements while preserving the ability to detect execution errors.
2Reliability
If lock-step verification technique is extended to many CPUs, then error detection coverage is improved, but hardware overhead becomes impossible or uneconomic to support
Solution Approach 1:
The patent implements a universal software-based error detection framework that can be applied to any number of CPUs without proportionally increasing hardware overhead. The software module serves multiple functions: it can detect errors across single or multiple CPUs, validate execution results, and adapt to different system configurations, making the solution economically viable for systems with many processors.
Solution Approach 2:
The patent introduces dynamic error detection where the intensity and frequency of verification can be adjusted based on system conditions. Rather than continuously monitoring all CPUs with fixed hardware comparators, the software can dynamically select which CPUs to monitor based on workload, criticality, and available resources, allowing scalable error detection coverage that adapts to system needs.
3Device complexity
If software-based lock-step technique is used to compare function results, then hardware overhead is reduced, but execution time increases due to multiple algorithm executions
Solution Approach 1:
The patent applies partial verification by selecting only critical functions or execution paths for software-based error detection rather than verifying every operation. The system can choose to monitor only high-risk or time-sensitive functions, performing software comparisons selectively to minimize the impact on overall execution time while still providing meaningful error detection coverage.
Solution Approach 2:
The patent implements preliminary error detection by validating execution results immediately upon completion rather than requiring full completion of multiple algorithm executions. The software module checks results as they become available and can early-terminate verification processes when confidence is established, reducing the time penalty compared to waiting for complete lock-step execution of all algorithms.
Data Source
AI summary
A data processing device provided with an error detection unit includes a processor arranged to support execution of an operation including a first sequence of instructions and execution of a second sequence of instructions implementing the operation, the first and second sequences of instructions generating, when in use, a first result and a second result, respectively. Configurable circuitry is also provided and arranged to support a repository to receive the first result and the second result following generation thereof. The configurable circuitry is configured as a function comparator unit arranged to compare the first and second results for consistency and to control further execution of the first implementation and the second implementation in response to a result of the comparison.