Configurable Fabric Circuit for NoC Testing Pin Constraints
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Solution Overview
Problem
The complexity and size of modern System-on-Chip (SoC) designs, particularly network-on-chip (NoC), pose challenges in testing due to limitations in accessing embedded cores, power handling, and the scarcity of low-speed test connections, leading to inefficient testing and repair processes.
Innovation Solution
A configurable fabric circuit (CFC) that intercepts signals, reconfigures itself to operate in different modes for testing, debugging, or monitoring, and adapts data speeds to facilitate efficient data delivery and processing between cores and external interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If structural vectors are used for testing embedded cores, then testing efficiency and quality assessment improve, but the number of package pins required increases and testing time increases
Solution Approach 1:
The patent segments the testing process by separating the test access mechanism (TAM) from the functional cores, allowing structural vectors to be delivered through dedicated scan chains without requiring additional package pins for each core's functional ports. This segmentation enables efficient testing while maintaining pin constraints.
Solution Approach 2:
The patent introduces an intermediary test access mechanism (TAM) that acts as a mediator between the external test equipment and the embedded cores. The TAM provides dedicated scan chains that deliver structural vectors to cores without requiring direct access to functional ports, thereby reducing pin requirements while maintaining testing efficiency.
2Reliability
If dedicated test access pathways are provided to all core functional ports, then complete core testing is enabled, but device complexity and pin requirements increase significantly
Solution Approach 1:
The patent implements a universal test access mechanism that can test any embedded core through standardized scan chains. Rather than providing dedicated pathways to each core's functional ports, the universal TAM can be configured to access any core, thereby reducing overall device complexity while maintaining complete testing capability.
Solution Approach 2:
The patent extracts the test access functionality from the functional core interfaces and places it in a separate, dedicated test access mechanism. This extraction allows cores to be tested through simplified scan chains without requiring access to their complex functional ports, thereby reducing device complexity while maintaining testing completeness.
3Measurement precision
If scan vectors are applied with 100% toggle rate for complete fault coverage, then testing quality improves, but power consumption exceeds IC handling capability
Solution Approach 1:
The patent applies partial toggle rates in scan chains rather than requiring 100% toggle rate for all vectors. By using configurable scan rates and selective vector application, the system achieves adequate fault coverage while keeping power consumption within IC handling capabilities.
Solution Approach 2:
The patent changes the toggle rate parameter of scan vectors from fixed 100% to configurable rates. This parameter change allows optimization between fault coverage quality and power consumption by adjusting the toggle rate according to specific testing requirements and power constraints.
4Quantity of substance
If functional pins are used for test interface, then pin count is reduced, but test data bandwidth is limited by pin speed constraints
Solution Approach 1:
The patent transitions from using functional pins operating at functional speeds to dedicated scan chain inputs operating at higher test speeds. This dimensional change in the test interface allows test data to be delivered at bandwidth rates independent of functional pin constraints, thereby increasing test data bandwidth without increasing pin count.
Data Source
AI summary
A method and system is provided for Network-on-Chip (NoC) and other integrated circuit architectures. A configurable fabric circuit (CFC) is interfaced with one or more core circuits and the CFC is responsive to an input signal and capable of reconfiguring the logic circuit in the CFC in accordance with an operational mode determined based on the received input signal to facilitate a core circuit interfaced therewith to carry out an operation consistent with the operational mode.