Configurable FEC Decoder for Low-Power Syndrome Computation
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Solution Overview
Problem
Conventional forward error correction decoding systems are power hungry, slow, and inflexible, consuming excessive power even when channel conditions allow for lower computational demands.
Innovation Solution
A low-power block code forward error correction decoder that dynamically adjusts the number of compute units based on channel conditions, using a systolic array architecture with configurable syndrome computation, key-equation solver, and Chien search circuitry to minimize power consumption while maintaining decoding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional forward error correction decoding systems are used, then decoding performance is maintained, but power consumption is excessive
Solution Approach 1:
The decoder dynamically adjusts the number of active syndrome compute units and processing elements based on channel conditions. When channel conditions are good, fewer compute units are activated, reducing power consumption. When channel conditions deteriorate, more compute units are activated to maintain decoding performance. This dynamic reconfiguration resolves the contradiction between power consumption and decoding performance.
Solution Approach 2:
The system changes operational parameters (number of active syndrome compute units, processing elements) based on channel quality metrics. By monitoring channel conditions and adjusting the activation threshold and number of active units, the system optimizes the balance between power consumption and decoding reliability for different operating scenarios.
2Adaptability or versatility
If fixed computational resources are allocated, then hardware design is simplified, but the system is inflexible to varying channel conditions
Solution Approach 1:
The decoder employs dynamic reconfiguration capabilities where the number of active syndrome compute units and processing elements can be adjusted based on channel conditions. This dynamic approach provides adaptability to varying channel conditions while using a modular architecture that manages hardware complexity through systematic organization of configurable resources.
Solution Approach 2:
The decoder is designed with universal compute units that can be dynamically configured to handle different decoding requirements. The same hardware resources (syndrome compute units, processing elements) serve multiple functions depending on channel conditions, providing versatility without requiring completely separate hardware for each operating mode.
3Productivity
If maximum computational resources are always active, then decoding speed is maintained, but power consumption increases
Solution Approach 1:
The decoder dynamically adjusts the number of active processing elements and syndrome compute units based on channel conditions and decoding requirements. When channel conditions are good and fewer corrections are needed, fewer processing elements are active, reducing power consumption while maintaining sufficient decoding speed. When errors increase, more processing elements are activated to maintain decoding throughput.
Solution Approach 2:
The system activates only the necessary number of compute units and processing elements required for the current channel conditions, rather than always running at maximum capacity. This partial action approach maintains adequate decoding speed for the actual workload while significantly reducing power consumption during favorable channel conditions.
Data Source
AI summary
A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.