Configurable FFT Pipeline Architecture for Multi-Size Processing
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Solution Overview
Problem
Current FFT pipeline architectures require multiple pipelines to support different FFT sizes, leading to increased chip area and cost, as they are designed for specific FFT size requirements, making them inefficient for applications needing multiple FFT sizes.
Innovation Solution
A configurable pipelined FFT architecture that uses multiplexers and adjustable computational elements to select appropriate stages and multiplication factors based on the required FFT size, allowing a single pipeline to process multiple FFT sizes efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple pipelines are used to support different FFT sizes, then the FFT size versatility is improved, but the chip area and cost increase
Solution Approach 1:
The patent implements a single FFT pipeline that can be configured to support multiple FFT sizes (e.g., 16, 32, 64, 128, 256, 512, 1024, 2048) through programmable control. The pipeline uses configurable parameters including FFT size, number of stages, parallel processing channels, and pipeline depth, all controlled via register files and control logic. This allows one physical pipeline to perform the function of multiple dedicated pipelines, achieving versatility without proportionally increasing chip area.
Solution Approach 2:
The FFT pipeline employs dynamic configuration capabilities where parameters such as FFT size, number of stages, and parallel processing channels can be adjusted at runtime through control registers. The pipeline depth and processing mode (single-pass or two-pass) are dynamically configurable, allowing the system to adapt to different application requirements without hardware reconfiguration. This dynamic adaptability enables a single fixed hardware structure to serve multiple FFT size requirements.
2Adaptability or versatility
If multiple pipelines are used to support different FFT sizes, then the FFT size versatility is improved, but the cost increases
Solution Approach 1:
The patent implements a single FFT pipeline that can be configured to support multiple FFT sizes (e.g., 16, 32, 64, 128, 256, 512, 1024, 2048) through programmable control. The pipeline uses configurable parameters including FFT size, number of stages, parallel processing channels, and pipeline depth, all controlled via register files and control logic. This allows one physical pipeline to perform the function of multiple dedicated pipelines, achieving versatility without proportionally increasing chip area.
Solution Approach 2:
The FFT pipeline employs dynamic configuration capabilities where parameters such as FFT size, number of stages, and parallel processing channels can be adjusted at runtime through control registers. The pipeline depth and processing mode (single-pass or two-pass) are dynamically configurable, allowing the system to adapt to different application requirements without hardware reconfiguration. This dynamic adaptability enables a single fixed hardware structure to serve multiple FFT size requirements.
3Area of stationary object
If a single pipeline is used for multiple FFT sizes, then chip area is reduced, but the ability to process different FFT sizes efficiently is worsened
Solution Approach 1:
The FFT pipeline employs dynamic configuration capabilities where parameters such as FFT size, number of stages, and parallel processing channels can be adjusted at runtime through control registers. The pipeline depth and processing mode (single-pass or two-pass) are dynamically configurable, allowing the system to adapt to different application requirements without hardware reconfiguration. This dynamic adaptability enables a single fixed hardware structure to serve multiple FFT size requirements.
Solution Approach 2:
The patent segments the FFT processing into multiple configurable stages within the pipeline, where each stage can be independently configured. The pipeline supports configurable parallel processing channels, allowing the same physical hardware to process multiple data streams simultaneously. This segmentation enables efficient throughput by allowing fine-grained control over the processing pipeline for different FFT size requirements.
4Adaptability or versatility
If configurable elements are added to support multiple FFT sizes, then the FFT size versatility is improved, but the device complexity increases
Solution Approach 1:
The FFT pipeline employs dynamic configuration capabilities where parameters such as FFT size, number of stages, and parallel processing channels can be adjusted at runtime through control registers. The pipeline depth and processing mode (single-pass or two-pass) are dynamically configurable, allowing the system to adapt to different application requirements without hardware reconfiguration. This dynamic adaptability enables a single fixed hardware structure to serve multiple FFT size requirements.
Solution Approach 2:
The patent introduces control logic and register files as intermediary components that manage the configuration of the FFT pipeline. These intermediaries receive high-level configuration parameters (FFT size, processing mode) and translate them into the appropriate stage configurations, multiplexer settings, and pipeline depth parameters. This abstraction layer simplifies the user interface while managing the underlying complexity of configuring multiple pipeline stages for different FFT sizes.
Data Source
AI summary
A device for performing a Fast Fourier Transform (FFT) on an input dataset includes an FFT pipeline having a first stage configured to receive the input dataset, a plurality of intermediate stages and a final stage, each stage having a stage input; a computational element; and a stage output; a controller configured to select a size for the FFT; and a multiplexer configured to: receive data output from one of the intermediate stages and data output from the final stage; select one of the received outputs in dependence on the selected FFT size; and output said selection as a result of the FFT on the input dataset.