Configurable Flip-Flop Circuits for Double Edge Triggered Data Rate
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Solution Overview
Problem
Configurable integrated circuits face challenges in efficiently transmitting multiple signals beyond the capacity of standard network-on-chip (NOC) and require reduced power consumption and physical wire tracks, especially in double-data-rate applications and design-for-test methodologies.
Innovation Solution
The implementation of programmable flip-flop circuits that can operate in double/dual edge triggered (DET) mode, single edge triggered (SET) mode, or scan mode, allowing for efficient data movement and reduced power consumption by sampling input signals at both rising and falling edges in DET mode, using half the number of wires, and supporting double-data-rate applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard single edge triggered (SET) flip-flops are used in NOC, then power consumption is reduced and interface is simplified, but the number of wires required increases and data rate is limited
Solution Approach 1:
The flip-flop circuit is designed with dynamic reconfigurability, allowing it to switch between SET mode and DET mode based on operational requirements. This is achieved through control signals that dynamically adjust the circuit's triggering behavior, enabling the system to adapt wire usage and data rate characteristics to match current performance needs.
Solution Approach 2:
The invention changes the fundamental operating parameter of the flip-flop from single-edge triggering to dual-edge triggering. By modifying the triggering mechanism to respond to both rising and falling edges of the clock signal, the circuit achieves double the data rate capability while maintaining the same physical wire infrastructure, effectively halving the wire requirements for a given data throughput.
2Quantity of substance
If DET mode is used to double data rate, then wire usage is reduced by 50%, but circuit complexity increases
Solution Approach 1:
The flip-flop circuit is designed to perform multiple functions within a single unified structure. It can operate in SET mode for standard applications, DET mode for high-performance applications requiring double data rate, and scan mode for testing and diagnostics. This multi-functionality is achieved through shared circuit elements that can be dynamically controlled to serve different operational modes, eliminating the need for separate dedicated circuits for each function.
Solution Approach 2:
The circuit incorporates dynamic control mechanisms that allow it to transition between different operational modes based on system requirements. Control signals dynamically enable or disable specific circuit paths and triggering mechanisms, allowing the same physical hardware to adapt its behavior and complexity level to match current operational needs, thereby managing complexity efficiently.
3Productivity
If DET mode is implemented for high bandwidth applications, then data rate doubles, but power consumption increases
Solution Approach 1:
The system employs dynamic mode switching that allows it to transition between SET mode and DET mode based on real-time performance requirements. When maximum data rate is needed, DET mode is activated despite higher power consumption. When power efficiency is prioritized, the system switches to SET mode. This dynamic adaptation enables optimal balance between performance and power consumption throughout system operation.
Solution Approach 2:
The DET mode operation inherently utilizes periodic action by sampling data on both rising and falling edges of the clock signal. This periodic dual-edge sampling achieves double the data rate compared to single-edge sampling, while the system can periodically switch between modes to manage power consumption based on workload demands.
Data Source
AI summary
A flip-flop circuit includes first and second storage circuits. The flip-flop circuit is configurable to store first values of a data signal in the first storage circuit in response to rising edges of a clock signal and to store second values of the data signal in the second storage circuit in response to falling edges of the clock signal during a double edge triggered mode. The flip-flop circuit is configurable to store third values of the data signal in the first storage circuit and to output the third values from the first storage circuit in response to the clock signal during a single edge triggered mode.