Configurable Gate Array Using 3D Writable Memory
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Solution Overview
Problem
Conventional configurable gate arrays are limited by fixed computing elements that cannot be reconfigured to perform complex math functions, restricting their application in high-performance computing and requiring larger die sizes and higher costs.
Innovation Solution
Incorporating three-dimensional writable memory (3D-W) to create configurable computing elements that can be electrically programmed with look-up tables for various math functions, allowing for reconfiguration and increased computing power while reducing die size through vertical stacking and substrate area savings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed computing elements are used in configurable gate arrays, then the circuit implementation is simple and manufacturing is easier, but the adaptability to perform complex math functions is limited
Solution Approach 1:
The computing elements are transformed from fixed to dynamic/reconfigurable. The patent implements computing elements that can be reconfigured to perform different math functions through programmable interconnects and configurable logic elements, allowing the same hardware to adapt to various computational requirements rather than being fixed for a single function.
Solution Approach 2:
The computing elements are designed to perform multiple functions. The patent creates a universal computing element that can realize any one of a plurality of math functions (addition, subtraction, multiplication, division, square root, etc.) depending on configuration signals, eliminating the need for separate dedicated circuits for each math function.
2Productivity
If fixed computing elements are used, then the device structure is simpler, but the die size is larger for the same computing power
Solution Approach 1:
By making computing elements universal and reconfigurable, the patent reduces the total number of computing elements needed. A single reconfigurable computing element can replace multiple fixed computing elements dedicated to different math functions, thereby reducing die size while maintaining or enhancing computing power.
Solution Approach 2:
The patent merges multiple fixed computing elements into a single reconfigurable computing element. By combining the functionality of addition, subtraction, multiplication, division, and other math functions into one programmable unit, the overall die area is reduced while preserving all required computational capabilities.
3Adaptability or versatility
If fixed computing elements are used, then manufacturing is easier, but adaptability for different applications is reduced
Solution Approach 1:
The patent incorporates configurable interconnects and logic elements during manufacturing that are pre-designed to enable reconfiguration. The manufacturing process includes building in the capability for future configuration through programmable connections, so that while the base structure is manufactured once, the adaptability is built-in from the start rather than requiring complex post-manufacturing modifications.
Data Source
AI summary
The present invention discloses a configurable gate array based on three-dimensional writable memory (3D-W). It comprises an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which is electrically programmable and can be loaded with a look-up table (LUT) for a math function.