Configurable Gate Driver for USB Type-C Power-FET Control

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Solution Overview

Problem

Electronic device manufacturers face challenges in designing devices that can efficiently support both N-channel and P-channel power-FETs due to the need for separate IC controllers, leading to longer design times, increased costs, and reduced flexibility in power path management.

Innovation Solution

A programmable/configurable integrated gate-driver circuit that supports three output states to control both N-channel and P-channel power-FETs, allowing for automatic detection and selection of the appropriate gate-driver output voltages, enabling a single-chip solution for various applications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate IC controllers are used for N-channel and P-channel power-FETs, then each controller can be optimized for its specific FET type, but device complexity and design time increase

Engineering Contradiction:
ImproveFET control optimizationVSAvoidcontroller quantity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate driver circuit is designed with configurable output states that can be programmed via I2C interface to support both N-channel and P-channel power-FETs. The circuit includes programmable pull-up/pull-down resistors and configurable output impedance that can be adjusted through register settings, allowing a single universal controller to replace multiple dedicated controllers while maintaining optimized control for each FET type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple gate-driver circuits are used to support both FET types, then each FET type receives dedicated control, but manufacturing cost increases

Engineering Contradiction:
ImproveFET control precisionVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the functionality of separate gate-driver circuits into a single integrated circuit that can be configured through software programming. The unified design consolidates multiple control paths, resistors, and switching elements into one chip, reducing component count, PCB real estate, and assembly costs while maintaining the ability to provide dedicated optimized control for both N-channel and P-channel FETs through configurable registers.

Inventive Principle:
Principle #5Merging (Combining)

3Device complexity

If a single-chip solution is used to control both FET types, then design complexity reduces, but the circuit must support multiple output states increasing its complexity

Engineering Contradiction:
Improvecontroller integrationVSAvoidoutput state flexibility
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The gate driver circuit implements dynamic configurability where output states, impedance levels, and control characteristics can be changed through software programming via I2C interface. Registers allow runtime reconfiguration of pull-up/pull-down strengths, output voltage levels, and control timing parameters, enabling the single chip to adapt to different FET types and application requirements without hardware changes or increased structural complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10802571B2Configurable and power-optimized integrated gate-driver for USB power-delivery and type-C SoCs
Publication Date: 2020.10.13 INFINEON TECHNOLOGIES AMERICAS CORP
  • US10802571B2 patent drawing
  • US10802571B2 patent drawing
  • US10802571B2 patent drawing

AI summary

Techniques for power-Field Effect Transistor (power-FET) gate drivers are described herein. In an example embodiment, a method for an USB-enabled system with an integrated circuit (IC) controller comprises: determining, by the IC controller, whether a first power path or a second power path is coupled to the IC controller, where the first power path comprises an external N-channel power-FET and the second power path comprises an external P-channel power-FET; turning and maintaining ON the external N-channel power-FET by the IC controller, when the first power path is determined as being coupled to the IC controller; and turning OFF the external N-channel power-FET and turning and maintaining ON the external P-channel power-FET by the IC controller, when the second power path is determined as being coupled to the IC controller.