Configurable GPU Hardware Switching Vertex Pixel Processing Paths

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Solution Overview

Problem

Conventional tile-based rendering (TBR) technologies in graphics processing units (GPUs) incur extra hardware costs and memory allocation requirements, leading to increased complexity and bandwidth usage compared to immediate rendering technologies.

Innovation Solution

A method and apparatus that utilize a configurable hardware circuit to switch between vertex processing and pixel processing paths within the GPU, allowing for efficient tile-based rendering operations without the need for additional hardware or memory resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional TBR technologies are used, then graphics processing performance is improved, but hardware complexity and cost increase

Engineering Contradiction:
Improvegraphics processing performanceVSAvoidhardware complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a unified rendering pipeline that can operate in both immediate rendering mode and tile-based rendering mode using the same hardware resources. The configurable hardware circuit can be dynamically switched between different processing paths (vertex processing path and pixel processing path) depending on the rendering mode, eliminating the need for separate dedicated hardware for each mode and thereby reducing hardware complexity while maintaining graphics processing performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If conventional TBR technologies are used, then graphics processing performance is improved, but memory allocation and bandwidth usage increase

Engineering Contradiction:
Improvegraphics processing performanceVSAvoidmemory allocation
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent merges the vertex processing functions and pixel processing functions into a single integrated rendering pipeline. By combining these previously separate processing stages into one unified path with configurable hardware, the system reduces the total memory allocation required and decreases bandwidth usage while maintaining graphics processing performance.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If separate VP path and PP path hardware are implemented, then processing capability is improved, but hardware cost increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidhardware cost
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent employs a dynamic configurable hardware circuit that can be reconfigured at runtime to perform different functions. The hardware is dynamically switched between vertex processing mode and pixel processing mode based on the current rendering phase, allowing a single hardware implementation to provide the versatility of multiple dedicated processing paths without incurring the cost of implementing all paths simultaneously.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9613392B2Method for performing graphics processing of a graphics system in an electronic device with aid of configurable hardware, and associated apparatus
Publication Date: 2017.04.04 XUESHAN TECH INC
  • US9613392B2 patent drawing
  • US9613392B2 patent drawing
  • US9613392B2 patent drawing

AI summary

A method for performing graphics processing of a graphics system in an electronic device and an associated apparatus are provided, where the method includes the steps of: configuring a configurable hardware of the graphics system to be a vertex processing (VP) path in a specific processing phase; utilizing the VP path to perform VP-related tile-based rendering (TBR) operations; configuring the configurable hardware of the graphics system to be a pixel processing (PP) path in another processing phase; and utilizing the PP path to perform PP-related TBR operations. For example, after performing VP-related TBR operations of a specific frame of a plurality of frames is completed, PP-related TBR operations of the specific frame are performed, where after performing the PP-related TBR operations of the specific frame is completed, VP-related TBR operations of another frame of the plurality of frames are performed.