Configurable IC Debugging via Separate Configuration Network
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing configurable integrated circuits (ICs) face challenges in debugging due to the need for debugging circuitry that either occupies valuable user design space or requires invasive designs, leading to inefficiencies and the inability to readily redesign debugging components without reconfiguring the entire IC.
Innovation Solution
A method is introduced to optimize user designs for configurable ICs, eliminating circuit elements and maintaining records to reconstruct data, allowing for monitoring and debugging without occupying user design space, using a separate configuration/debug network that separates debugging functions from user design circuits, enabling non-invasive debugging and efficient data routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If debugging circuitry is integrated into the main body of the integrated circuit using basic configurable circuits, then debugging functionality is achieved, but configurable circuits that could otherwise be used for implementing user design are occupied
Solution Approach 1:
The patent segments the integrated circuit into distinct functional areas: a configurable logic array for user designs and a separate configuration/debug network for debugging operations. This segmentation allows the debugging circuitry to be physically separated from the user design circuits, enabling independent optimization of each function without compromising the other.
Solution Approach 2:
The patent extracts the debugging circuitry from the configurable logic array by implementing a separate configuration/debug network that is physically distinct from the user design circuits. This extraction removes the harmful effect of debugging circuits occupying user design space while preserving debugging functionality through dedicated routing paths and memory elements.
2Reliability
If debugging circuitry is implemented as fixed function circuitry located among configurable circuits, then debugging capability is provided, but the debugging circuitry cannot be readily redesigned and requires invasive designs
Solution Approach 1:
The patent implements dynamic reconfigurability in the debugging system by allowing the configuration/debug network to be dynamically configured through programming of configuration memory elements. This enables the debugging circuitry to adapt its structure and connectivity based on different user designs without requiring physical redesign, providing both debugging capability and redesign flexibility.
Solution Approach 2:
The patent creates a universal debugging infrastructure that can support multiple user designs through a single configurable architecture. The configuration/debug network serves multiple functions: it provides debugging capabilities for various user designs, enables non-invasive monitoring, and allows flexible redesign through reconfiguration, eliminating the need for invasive designs for each user application.
3Adaptability or versatility
If configuration data is stored in SRAM cells within the configurable logic array, then configuration flexibility is achieved, but the storage capacity for configuration data is limited by the logic array size
Solution Approach 1:
The patent resolves the storage capacity limitation by transitioning from two-dimensional storage within the logic array to a separate three-dimensional storage architecture. Configuration memory elements are placed in dedicated memory blocks outside the configurable logic array, allowing configuration data storage to scale independently from the logic array size and providing virtually unlimited configuration flexibility.
Data Source
AI summary
Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.