Configurable IC Memory Hierarchy via Offset Connections
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Solution Overview
Problem
Configurable integrated circuits (ICs) face challenges in efficiently connecting multiple logic circuits and managing multiple memory ports accessing the same memory location, leading to issues like blocked circuits, ambiguous results, and timing problems due to the limitations of existing interconnect circuits and memory port prioritization.
Innovation Solution
The implementation of non-neighboring offset connections (NNOCs) and a port priority hierarchy in configurable ICs allows for direct connections between non-adjacent tiles and prioritizes memory port accesses, enabling efficient data path shifting and multiple memory accesses per user cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory ports access the same memory location simultaneously, then memory bandwidth and parallelism are improved, but ambiguous results and timing conflicts occur
Solution Approach 1:
The patent implements a dynamic priority arbitration mechanism where memory port priorities can be dynamically assigned and changed based on operational needs. The priority encoder continuously evaluates multiple port requests and dynamically selects the highest priority port for memory access, allowing the system to adapt to different access patterns and resolve conflicts without ambiguity.
Solution Approach 2:
The patent employs feedback mechanisms through priority signals that are generated based on the current state of memory access requests. The priority encoder receives feedback from multiple port request signals and produces a selected port output that reflects the current highest priority request, creating a closed-loop control system that prevents ambiguous simultaneous accesses.
2Ease of manufacture
If traditional interconnect circuits are used to connect logic circuits, then circuit layout is simplified, but blocked circuits and routing limitations occur
Solution Approach 1:
The patent introduces offset connections that operate in an additional spatial dimension beyond traditional adjacent tile connections. By allowing connections between non-adjacent tiles with offset positioning, the interconnect structure gains enhanced routing capability without complicating the basic tile layout, enabling data to bypass blocked regions and access distant logic circuits efficiently.
Solution Approach 2:
The patent segments the interconnect system into multiple independent connection types: adjacent tile connections for local communication and offset connections for long-range communication. This segmentation allows each connection type to be optimized independently, maintaining simple local routing while adding versatile long-range routing capability through separate offset connection pathways.
3Device complexity
If adjacent tile connections are used for data transfer, then connection complexity is reduced, but data path shifting and long-distance communication become inefficient
Solution Approach 1:
The patent adds an offset dimension to the connection topology, allowing direct connections between tiles that are not immediately adjacent. This dimensional extension enables data to skip intermediate tiles and reach distant destinations in fewer steps, dramatically improving transfer speed for long-distance communication without adding complex routing logic to the basic connection structure.
Data Source
AI summary
Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions specify the effects of accesses to a memory by a set of memory ports given a set of parameters chosen by the user.